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hynix semiconductor inc. 8-bit single-chip microcontrollers hms81c4x60 users manual (ver. 1.1)
version 1.1 published by mcu application team heung-il bae(hibae@hynix.com), byoung-jin lim( bjinlim@hynix.com) 2 0 0 1 hynix semiconductor inc. all rights reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and repre- sentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
hms81c4x60 november 2001 ver 1.1 1 hms81c4x60 cmos single-chip 8-bit microcontroller for television 1. overview 1.1 description the hms81c4x60 is an advanced cmos 8-bit microcontroller with 60k bytes of rom. this is one of the hms800 family. this is a powerful microcontroller which provides a high flexibility and cost effective solution to many tv applications. the hms81c4x60 provides following standard features: 60k bytes of rom, 1024 bytes of ram, 8/16-bit timer/counter, on- chip pll oscillator and clock circuitry. in addition, there are other package types, hms81c4360(32pdip), HMS81C4360SK(32skdip), hms81c4460(42sdip). this document is explained for the base of hms81c4x60, the eliminated functions are same as below. 1.2 features ? 60k bytes of on-chip program memory ? 1024 bytes of on-chip data ram ? minimum instruction cycle time - 256ns (nop operation) ? pll oscillator for osd and system clock - external 4mhz crystal input ? 31 programmable i/o pins - 26 input/output and 5 input pins ?i 2 c bus interface - multimaster (2 pairs interface pins) ? a/d converter - 8-bit 5 ch ? pulse width modulation - 14-bit 1 ch - 8-bit 5 ch ?timer - timer/counter : 8-bit 4 ch(16-bit 2 ch) - basic interval timer - watch dog timer ? number of interrupt source - 16 interrupts - 3 external interrupts ?on screen display - 512 character fonts pattern - character size : 1.0, 1.5, 2.0 times - character pixel size : 12 10, 12 12, 12 14, 12 16, 16 18 - display capability : 48 characters 16 lines - character, background color : 512 colors, 8 pal- let - special functions : rounding, outline, shadow, underline, double scanned line osd ? buzzer driving port - 500hz ~ 250khz @4mhz (duty 50%) ? vertical blanking interveral information cap- ture for eia-608(closed caption) or vps, etc device name rom size eprom size ram size i/o package hms81c4260 60k bytes - 1024bytes 31 52sdip hms87c4260 60k bytes 1024bytes 31 52sdip
hms81c4x60 2 november 2001 ver 1.1 1.3 development tools note: there are several setting switches in the emulator. user should read carefully and do setting properly before developing the program. otherwise, the emulator may not work properly. the hms87c4x60 is supported by a full-featured macro assem- bler, an in-circuit emulator choice-dr. tm and eprom pro- grammers. there are two different type programmers such as single type and gang type. for more detail, refer to eprom pro- gramming chapter. macro assembler operates under the ms- windows 95/98 tm . please contact sales part of hynix semiconductor. 1.4 ordering information device name rom size (bytes) ram size package mask rom version hms81c4260 60k bytes 1024 bytes 52sdip otp rom version hms87c4260 60k bytes eprom (otp) 1024 bytes 52sdip mask rom version HMS81C4360SK 60k bytes 1024 bytes 32skdip otp rom version hms87c4360sk 60k bytes eprom (otp) 1024 bytes 32skdip mask rom version hms81c4360 60k bytes 1024 bytes 32pdip otp rom version hms87c4360 60k bytes eprom (otp) 1024 bytes 32pdip mask rom version hms81c4460 60k bytes 1024 bytes 42sdip otp rom version hms87c4460 60k bytes eprom (otp) 1024 bytes 42sdip
hms81c4x60 november 2001 ver 1.1 3 2. block diagram figure 2-1 block diagram pwm i 2 c timer prescaler /bit watch dog buzzer remocon interrupt g8mc core r4 port ram ( 1024) mask rom ( user rom : 60kb font rom : 32kb ) pll clock adc data osd r10/an0 r11/an1 r12/an2 r13/an3 r14/an4 r30/pwm0 r31/pwm1 r32/pwm2 r33/pwm3 r34/pwm4 r35/pwm5 r40/scl0 r41/sda0 r42/scl1 r43/sda1 r24/ec2 r25/ec3 cvbs r g b ym ys r36/buz r37/tmr1 r21/int1 r22/int2 vs hs test vdd reset xin xout vss scap r3 port r2 port r1 port r0 port controller timer generation / system controller slicer r40 ~ r43 r30 ~ r37 r20 ~ r25 r10 ~ r14 r00 ~ r07 r23/int3
hms81c4x60 4 november 2001 ver 1.1 3. pin assignment figure 3-1 52sdip r30/pwm0 r31/pwm1 ys ym r32/pwm2 r33/pwm3 r34/pwm4 r35/pwm5 r36/buz r37/tmr1 test vss b g r vdd vss xin xout reset r03 r40/scl0 r41/sda0 cvbs scap r42/scl1 r43/sda1 r04 r05 r06 r07 vdd r14/ad4 vdd vss r10/ad0 r11/ad1 r12/ad2 r13/ad3 hs vs r20 1 2 12 11 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 52 51 41 42 50 49 48 47 46 45 44 43 40 39 38 37 36 35 34 33 32 hms81c4260 r21/int1 r22/int2 r23/int3 r24/ec2 r25/ec3 22 23 24 25 26 r02 vdd vss r01 r00 31 30 29 28 27 52sdip
hms81c4x60 november 2001 ver 1.1 5 figure 3-2 42sdip r31/pwm1 r32/pwm2 g b r33/pwm3 r34pwm4 r35/pwm5 r36/buz r37/tmr1 test ym ys r xin xout reset r03 r02 r01 r00 r25/ec3 r40/scl0 r41/sda0 r10/ad0 vss r42/scl1 r43/sda1 r04 vdd r14/ad4 scap cvbs vdd r11/ad1 r12/ad2 r13/ad3 hs vs r21/int1 r22/int2 r23/int3 r24/ec2 1 2 12 11 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 42 41 31 32 40 39 38 37 36 35 34 33 30 29 28 27 26 25 24 23 22 hms81c4460 42sdip
hms81c4x60 6 november 2001 ver 1.1 figure 3-3 32skdip figure 3-4 32pdip HMS81C4360SK r33/pwm3 r34/pwm4 xout xin r35/pwm5 r37/tmr1 test ym ys b g r reset r02 r24/ec2 r23/int3 r40/scl0 r41/sda0 r13/ad3 r10/ad0 r42/scl1 r43/sda1 vdd r14/ad4 scap cvbs vdd vss hs vs r21/int1 r22/int2 1 2 12 11 3 4 5 6 7 8 9 10 13 14 15 16 32 31 21 22 30 29 28 27 26 25 24 23 20 19 18 17 32skdip hms81c4360 r34pwm4 r35pwm5 reset xout r37/tmr1 test ym ys b g r xin r02 r24/ec2 r23/int3 r21/int1 r40/scl0 r41/sda0 r11/ad1 r10/ad0 r42/scl1 r43/sda1 vdd r14/ad4 scap cvbs vdd vss r12/ad2 r13/ad3 hs vs 1 2 12 11 3 4 5 6 7 8 9 10 13 14 15 16 32 31 21 22 30 29 28 27 26 25 24 23 20 19 18 17 32pdip
hms81c4x60 november 2001 ver 1.1 7 4. package diagram unit: mm hynix hms81c4260 1 26 27 52 45.97 0.13 0.76 0.13 1.778 0.25 4.38 max. 13.97 0.25 15.24 0.25 0.47 0.13 1.02 0.25 3.81 0.13 3.24 0.20 0.50 min. 0.25 0.05 0 ~ 15 1.665 0.015 0.065 0.1 bsc typ 0.600 bsc 0.550 0 . 0 1 2 0 ~ 15 min 0.015 0.140 0.530 0 . 0 0 8 0.2 max 0.045 0.022 0.120 hynix hms81c4360 1.645 1 16 17 32 unit: inch
hms81c4x60 8 november 2001 ver 1.1 figure 4-1 package diagram unit: mm hynix hms81c4460 1 21 22 42 36.83 0.13 0.76 0.13 1.778 0.25 4.38 max. 13.97 0.25 15.24 0.25 0.47 0.13 1.02 0.25 3.81 0.13 3.24 0.20 0.50 min. 0.25 0.05 0 ~ 15 unit: mm hynix HMS81C4360SK 1 16 17 32 27.68 0.13 0.76 0.13 1.778 0.25 4.38 max. 10.16 0.25 8.89 0.25 0.47 0.13 1.02 0.25 3.81 0.13 3.24 0.20 0.50 min. 0.25 0.05 0 ~ 15
hms81c4x60 november 2001 ver 1.1 9 5. pin function v dd : supply voltage. v ss : circuit ground. test : used for shipping inspection of the ic. for normal operation, it should not be connected . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r10~r14 : r1 is a 5-bit read only port. r1 pins 1 or 0 writ- ten to the port direction register can be used as inputs. in addition, r1 serves the functions of the various follow- ing special features. r20~r25 : r2 is a 6-bit cmos bidirectional i/o port. each pins 1 or 0 written to the their port direction register can be used as outputs or inputs. in addition, r2 serves the functions of the various follow- ing special features. r30~r37 : r3 is 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r3 serves the functions of the various follow- ing special features. r40~r43 : r4 is a 4-bit open drain i/o port. each pins 1 or 0 written to the their port direction register can be used as outputs or inputs. in addition, r4 serves the functions of the various follow- ing special features. r,g,b : r,g,b are output port. each pins controls red, green, blue color control. ym,ys : ym,ys are cmos output port. each pins con- trols background, edge control. hs,vs : hs,vs are cmos input port. each pins vertical sync. input and horizaltal sync. inputs. cvbs : cvbs is a cvbs(composit video in) signal input pin. port pin alternate function r10 r11 r12 r13 r14 ad0 (a/d converter input 0) ad1 (a/d converter input 1) ad2 (a/d converter input 2) ad3 (a/d converter input 3) ad4 (a/d converter input 4) port pin alternate function r21 r22 r23 r24 r25 int1 (external interrupt input 1) int2 (external interrupt input 2) int3 (external interrupt input 3) ec2 (event counter input 2) ec3 (event counter input 3) port pin alternate function r30 r31 r32 r33 r34 r35 r36 r37 pwm0 (pulse width modulation output 0) pwm1 (pulse width modulation output 1) pwm2 (pulse width modulation output 2) pwm3 (pulse width modulation output 3) pwm4 (pulse width modulation output 4) pwm5 (pulse width modulation output 5) with 14bit resolution buz (buzzer output) tmr1 (timer interrupt 1) port pin alternate function r40 r41 r42 r43 scl0 (i 2 c clock 0) sda0 (i 2 c data0) scl1 (i 2 c clock 1) sda1 (i 2 c data 1) pin name pin no. in/out function v dd 9,13,30, 37 - supply voltage v ss 14,29, 36,43 - circuit ground table 5-1 port function description
hms81c4x60 10 november 2001 ver 1.1 test 44 i test signal input (internal pull up resister) reset 33 i reset signal input x in 35 i main oscillation input x out 34 o main oscillation output hs 19 i horisontal sync. input vs 20 i vertical sync. input r 38 o red signal output g 39 o green signal output b 40 o blue signal output ys 41 o edge signal output ym 42 o background signal output r30/pwm0 52 i/o pwm functions 8bit pwm (pull up) r31/pwm1 51 i/o 8bit pwm (pull up) r32/pwm2 50 i/o 8bit pwm (pull up) r33/pwm3 49 i/o 8bit pwm (pull up) r34/pwm4 48 i/o 8bit pwm r35/pwm5 47 i/o 14bit pwm r36/buz 46 i/o buzzer (pull up) r37/tmr1 45 i/o timer interrupt 1 r40/scl0 1 i/o i 2 c functions (open drain) i 2 c serial clock 0 r41/sda0 2 i/o i 2 c serial data 0 r42/scl1 3 i/o i 2 c serial clock 1 r43/sda1 4 i/o i 2 c serial data 1 r20 21 i/o external interrupt functions (pull up) r21/int1 22 i/o external interrupt input 1 r22/int2 23 i/o external interrupt input 2 (pull up) r23/int3 24 i/o external interrupt input 3 r24/ec2 25 i/o event counter input 2 r25/ec3 26 i/o event counter input 3 (pull up) scap 11 i data slicer comparation reference voltage r10/ad0 15 i a/d conversion functions analog input 0 r11/ad1 16 i analog input 1 r12/ad2 17 i analog input 2 r13/ad3 18 i analog input 3 r14/ad4 10 i analog input 4 cvbs 12 i composit video input pin name pin no. in/out function table 5-1 port function description
hms81c4x60 november 2001 ver 1.1 11 r00 27 i/o digital i/o functions (normal i/o, pull up) r01 28 i/o (normal i/o, pull up) r02 31 i/o (normal i/o) r03 32 i/o (normal i/o, pull up) r04 5 i/o (open drain, pull up) r05 6 i/o (open drain, pull up) r06 7 i/o (open drain, pull up) r07 8 i/o (open drain, pull up) pin name pin no. in/out function table 5-1 port function description
hms81c4x60 12 november 2001 ver 1.1 6. port structures x in , x out r03~r00,r37~r30,hs,vs,ys,ym r14~10, cvbs r07~r04, r43~r40, test x in x out v ss v dd v ss v dd main frequency clock v dd v ss stop v ss pin v dd v ss v dd v ss i/o data out data in data in out enable schmitt ? { pin v dd v ss v dd v ss i data out data in data in out enable schmitt ? { analog in analog in pin out enable v ss data in data in data out schmitt ? { i/o v dd v ss
hms81c4x60 november 2001 ver 1.1 13 r,g,b r25~r20, reset scap pin v dd v ss i/o v dd v ss pin v dd v ss v dd v ss i/o data out data in data in out enable schmitt ? { noise filter pin i/o v dd v ss data in
hms81c4x60 14 november 2001 ver 1.1 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +6.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of vss pin.........................160 ma maximum current into v dd pin ..........................160 ma maximum current sunk by(i ol per i/o pin) .........20 ma maximum output current sourced by (i oh per i/o pin) .................................................................................8 ma maximum current ( s i ol ) .................................... 100 ma maximum current ( s i oh )...................................... 80 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 dc electrical characteristics (t a =-10~70 c, v dd =4.5~5.5v) , parameter symbol condition specifications unit min. max. supply voltage v dd v dd =4.5~5.5v 4.5 5.5 v operating frequency f xin f xin =4mhz -4.0(typical)mhz operating temperature t opr -10 70 c parameter symbol condition specifications unit min. typ. max. high level input voltage v ih test , reset , xin, r0, r1, r2, r3, hs, vs 0.8 v dd - v dd v low level input voltage v il test , reset , xin, r0, r1, r2, r3,r4 hs, vs 0- 0.12 v dd v high level output voltage v oh i oh = -5ma r0, r1, r2, r3, ys, ym v dd - 1 --v low level output voltage v ol i ol = 5ma r0, r1, r2, r4 - -1.0v supply current in active mode i dd v dd -4080ma pull-up lekage current i rup v dd = 5.5v, v pin = 0.4v test , r00, r01, r03, r04, r05, r06, r07, r20, r22, r25, r30, r31, r32, r33 r36 -1.5 -400 m a high input leakage current i izh v dd = 5.5v , v pin = v dd all input, i/o pins except x in -5 - 5 m a
hms81c4x60 november 2001 ver 1.1 15 7.4 ac characteristics (t a =-10~70 c, v dd =5v 10% , v ss =0v) low input leakage current i izl v dd = 5.5v , v pin = 0v all input, i/o pins except x in , osc1 -5 - 5 m a ram data retention voltage v ram v dd 1.2 - - v hysterisis vt+ ~ vt- test , reset , xin, hs, vs, r07 ~ r00, r21, r23, r24, r25, r37 ~ r30 1.0 - - v comparator operating range v rcvbs v dd = 5v cvbs pin 1.2 - 3.5 v comparator resolution v acvbs v dd = 5v cvbs pin - - 0.08 v rgb dac resolution 1 rgb r1 v dd = 5v no in/out current in r,g,b pin --5% rgb dac output voltage v rgb rgb dac on no in/out current in r,g,b pin v level 0 3/40v dd level 1 5/40v dd level 2 8/40v dd level 3 12/40v dd level 4 17/40v dd level 5 23/40v dd level 6 30/40v dd level 7 38/40v dd rgb v oh v ohrgb v dd = 5v rgb dac on level 7 i oh = -3ma 3.1 3.5 3.9 v rgb v ol v olrgb v dd = 5v rgb dac on level 0 i ol = 3ma 0.4 0.6 0.8 v parameter symbol condition specifications unit min. typ. max. parameter symbol pins specifications unit min. typ. max. crystal oscillator frequency f xin x in 345mhz external clock pulse width t mcpw x in 180 - 350 ns t scpw s clk 0.5 - m s external clock transition time t mrcp, t mfcp x in - - 20 ns t srcp, t sfcp s clk - - 20 ns
hms81c4x60 16 november 2001 ver 1.1 figure 7-1 timing chart oscillation stabilizing time t st x in , x out --20ms interrupt pulse width t iw int1~3 2 - - t sys 1 reset input width t rst reset 8- - t sys 1 event counter input pulse width t ecw ec2, ec3 2 - - t sys 1 event counter transition time t rec, t fec ec2, ec3 - - 20 ns 1. t sys is one of 1/f xin main clock operation mode, parameter symbol pins specifications unit min. typ. max. t mrcp t mfcp x in int1 ~ 3 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset t rec t fec 0.2v dd 0.8v dd ec2, ec3 t iw t iw t rst t ecw t ecw 1/f xin t mcpw t mcpw
hms81c4x60 november 2001 ver 1.1 17 7.5 a/d converter characteristics (ta=25 c, v dd =5v, v ss =0v) parameter symbol condition specifications unit min. typ. max. analog input voltage range v an - v ss -0.3 - v dd +0.3 v overall accuracy cain - - 1.5 2.5 lsb non linearity error nnle - - 1.5 2.5 differential non linearity error ndnle - - 1.5 2.5 zero offset error nzoe - - 0.5 2.0 full scale error nfse - - 0.75 1.0 gain error nge - - 1.5 2.0 conversion time tconv f main =4mhz --15 m s
hms81c4x60 18 november 2001 ver 1.1 7.6 typical characteristics these graphs and tables are for design guidance only and are not tested or guaranteed. in some graphs or tables, the datas presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data is a statistical summary of data collected on units from different lots over a period of time. typical repre- sents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation i ol - v ol , v dd =5.2v (ma) i ol 1.0 3.0 2.0 v ol (v) i oh - v oh , v dd =5.2v -8 -6 -4 -2 0 (ma) i oh 2.0 3.0 v oh (v) 70 c f main =4mhz v dd - v ih 4 3 2 1 0 (v) v ih1 44.5 55.5 6 v dd (v) ta=25 c 40 30 10 -10 -12 -14 4.0 20 f main =4mhz v dd - v ih 4 3 2 1 0 (v) v ih2 44.5 55.5 6 v dd (v) ta=25 c hysterisis -16 5.0 25 c -20 c 4.0 -20 c 70 c 25 c
hms81c4x60 november 2001 ver 1.1 19 ta= -20~70 c (main-clock) ta=25 c i dd1 - v dd 60 50 40 30 20 (ma) i dd 44.555.56 v dd (v) normal mode (main opr.) 6 4 2 1 0 (mhz) f main 44.555.5 6.5 v dd (v) operating area f main =4mhz 5 3 6 f main =4mhz v dd - v il 3 2 1 (v) v il1 44.5 55.5 6 v dd (v) ta=25 c hysterisis f main =4mhz v dd - v il 3 2 1 (v) v il1 44.5 55.5 6 v dd (v) ta=25 c
hms81c4x60 20 november 2001 ver 1.1 8. memory organization the gms81c4x60 has separate address spaces for pro- gram memory, data memory and display memory. pro- gram memory can only be read, not written to. it can be up to 60k bytes of program memory. data memory can be read and written to up to 1024 bytes including the stack ar- ea. font memory has prepared 32k bytes for osd. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers: in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer: the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 00 h to ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. normally, the initial value of ff h is used. program counter: the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word: the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a ya 16-bit register y a y a caution: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ? ff h sp 1 stack address (00 h ~ ff h ) 15 0 87 hardware fixed
hms81c4x60 november 2001 ver 1.1 21 [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned by rpr register (address 0f3 h ). it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds + 127 (7f h ) or - 128 (80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is addressed by rpr
hms81c4x60 22 november 2001 ver 1.1 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01bf sp after execution sp before execution 01bd 01be 01bd 01bc 01bf push down at acceptance of interrupt pcl pch 01bf 01bc 01be 01bd 01bc 01bf push down psw at execution of ret instruction pcl pch 01bf 01bf 01be 01bd 01bc 01bd pop up at execution of reti instruction pcl pch 01bf 01bf 01be 01bd 01bc 01bc pop up psw 0100 h 01bf h stack depth at execution of push instruction a 01bf 01be 01be 01bd 01bc 01bf push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01bf 01bf 01be 01bd 01bc 01be pop up pop a (x,y,psw)
hms81c4x60 november 2001 ver 1.1 23 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 60k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5 shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each area is assigned a fixed loca- tion in program memory. program memory area contains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 1, for example, is assigned to loca- tion 0fff8 h . the interrupt service locations spaces 2-byte interval: 0fff6 h and 0fff7 h for external interrupt 2, 0ffe8 h and 0ffe9 h for external interrupt 3, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area program memory tcall area interrupt vector area 1000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area lda #5 tcall 15 ; 1byte instruction :; instead of 2 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe i 2 c bus interface interrupt vector - basic interval timer interrupt vector watchdog timer interrupt vector timer/counter 3 interrupt vector timer/counter 1 interrupt vector v-sync interrupt vector timer/counter 2 interrupt vector timer/counter 0 interrupt vector external interrupt 2 vector on screen display interrupt vector - reset vector external interrupt 1 vector slicer interrupt vector external interrupt 3/4 vector "-" means reserved area. note:
hms81c4x60 24 november 2001 ver 1.1 figure 8-7 pcall and tcall memory area pcall ? rel 4f35 pcall 35 h tcall ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h ? 0d125 h reverse ? : index address
hms81c4x60 november 2001 ver 1.1 25 example: the usage software example of vector address and the initialize part. org 0ffe0h dw i2c_int dw not_used dw bit_int dw wdt_int dw ir_int dw timer3 dw timer1 dw vsync_int dw slice_int dw t2_int dw t0_int dw ext2_int dw ext1_int dw osd_int dw not_used dw reset org 0f000h ;******************************************** ; main program * ;******************************************** ; reset: di ;disable all interrupts clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000 h ->!00bf h ) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0ffh ;stack pointer initialize txsp ; ldm pllc,#0000_0101b ;16mhz system clock ; ldm r0, #0ffh ;normal port 0 ldm r0dir,#0ffh ;normal port direction : : ldm tm0,#0000_0000b ;timer stop : : call vram_clr ;clear vram : :
hms81c4x60 26 november 2001 ver 1.1 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into four groups, a user ram, control registers, stack, and osd memory. figure 8-8 data memory map user memory the gms81c4x60 has 1,024 8 bits for the user memory (ram) except peripheral reg. (64 bytes) . control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#05h ;divide ratio ? 8 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 22. page0 ram (192 bytes) peripheral reg. (64 bytes) 0100h 00c0h 0000h ram (256 bytes) 0200h ram (256 bytes) 0300h ram (256 bytes) 0400h 0500h 0600h ram (64 bytes) 0a00h osd ram (192 bytes) 0ac0h peripheral reg. (32 bytes) page1 page2 page3 page4 page5 page6 pagea stack area not used ram (slicer ram) ( 256 byte) 0b00h osd ram (192 bytes) 0bc0h peripheral reg. (32 bytes) pageb not used 0c00h 0fffh not used 0700h not used 0440h address symbol r/w reset value addressin g mode 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh r0 r0dd r1 r1dd r2 r2dd r3 r3dd r4 r4dd reserved reserved reserved reserved func pllc r/w w r w r/w w r/w w r/w w - - - - w w ???????? 00000000 ???????? ---00000 ???????? --000000 ???????? 00000000 ???????? ----0000 - - - - 0000000- -0000000 byte, bit 1 byte 2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte - - - - byte byte table 8-1control registers
hms81c4x60 november 2001 ver 1.1 27 0d0h 0d1h 0d2h 0d3h 0d4h 0d5h 0d6h 0d6h 0d7h 0d8h 0d9h 0dah 0dbh 0dch 0deh 0dfh tm0 tm2 tdr0 tdr1 tdr2 tdr3 bitr ckctlr wdtr icar icdr icsr iccr reserved reserved reserved r/w r/w r/w r/w r/w r/w r w w r/w r/w r/w r/w - - - -0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 0001000- 00000000 - - - byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit - - - 0e0h 0e1h 0e2h 0e3h 0e4h 0e5h 0e6h 0e7h 0e8h 0e9h 0eah 0ebh 0ech 0edh 0eeh 0efh pwmr0 pwmr1 pwmr2 pwmr3 pwmr4 pwmr5h pwmr5l reserved reserved reserved pwmcr1 pwmcr2 reserved reserved reserved aips w w w w w r/w r/w - - - r/w r/w - - - w ???????? ???????? ???????? ???????? ???????? ???????? --?????? - - - 00000000 -----000 - - - --000000 byte byte byte byte byte byte byte, bit - - - byte, bit byte, bit - - - byte 0f0h 0f1h 0f2h 0f3h 0f4h 0f5h 0f6h 0f7h 0f8h 0f9h 0fah 0fbh 0fch 0fdh 0feh 0ffh adcm adr ieds imod ienl irql ienh irqh reversed idcr idfs idr dpgr tmr reserved reserved r/w r w r/w r/w r/w r/w r/w - r/w r r r/w w - - ???????? ???????? --000000 --000000 00000000 00000000 00000000 00000000 - 0000-000 1----001 ???????? ----0000 ???????? - - byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit - byte, bit byte byte byte, bit byte - - table 8-1control registers 0ad0 0ad1 0ad2 0ad3 0ad4 0ad5 0ad6 0ad7 0ad8 0ad9 0ada 0adb 0adc 0add 0ade 0adf red0 red1 red2 green0 green1 green2 blue0 blue1 blue2 reserved reserved reserved reserved reserved reserved reserved w w w w w w w w w - - - - - - - ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? - - - - - - - byte, bit- byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit - - - - - - - 0ae0h 0ae1h 0ae2h 0ae3h 0ae4h 0ae5h 0ae6h 0ae7h 0ae8h 0ae9h 0aeah 0aebh 0aech 0aedh 0aeeh 0aefh 0af0h 0af1h 0af2h 0af3h 0af4h 0af5h 0af9h osdcon1 osdcon2 osdcon3 fdwset edgecol chedcl osdln lhpos dllmod dlltst l1attr l1eatr l1vpos l2attr l2eatr l2vpos winsh winsy wineh winey vcnt hcnt cultad r/w r/w w w w w r w w r w w w w w w w w w w r r w 00000000 00000000 00000000 01111010 10000111 ???????? ---00000 ???????? 00000000 --000000 ??????-? ---????? ???????? ???????? ---????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte, bit byte, bit byte byte, bit byte, bit byte, bit byte byte byte byte byte byte byte 0be0h 0be1h 0be2h 0be3h 0be4h 0be7h 0be8h slcon slinf0 slinf1 rikst riked sncst snced r/w w w w w w w 00000000 00000000 00000000 ???????? ???????? ???????? ???????? byte, bit byte, bit byte, bit byte byte byte byte 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clear- ing bit. table 8-1control registers
hms81c4x60 28 november 2001 ver 1.1 8.4 addressing mode the gms81c4x60 uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: fe0435 adc #35 h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1, rpr=01 h e45535 ldm 35 h ,#55 h (3) direct page addressing ? dp in this mode, a address is specified within direct page. example; g=0 e551: c535 lda 35 h ;a ? ram[35 h ] (4) absolute addressing ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; f100: 0735f0 adc !0f035 h ;a ? rom[0f035 h ] 35 a+35 h +c ? a 04 memory e4 0f100 h data ? 55 h ~ ~ ~ ~ data 0135 h t 35 0f102 h 55 0f101 h data 35 35 h 0e551 h data ? a t ~ ~ ~ ~ c5 0e550 h t : direct page 07 0f100 h ~ ~ ~ ~ data 0f035 h t f0 0f102 h 35 0f101 h a+data+c ? a address: 0f035
hms81c4x60 november 2001 ver 1.1 29 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag and rpr. f100: 981501 inc !0115 h ;a ? rom[115 h ] (5) indexed addressing x indexed direct page (no offset) ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1, rpr=01 h e550: d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h f100: db lda {x}+ x indexed direct page (8 bit offset) ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h e550: c645 lda 45 h +x 98 0f100 h ~ ~ ~ ~ data 115 h t 01 0f102 h 15 0f101 h data+1 ? data ? address: 0115 data d4 115 h 0e550 h data ? a t ~ ~ ~ ~ data db 35 h data ? a t ~ ~ ~ ~ 36h ? x data 45 3a h 0e551 h data ? a t ~ ~ ~ ~ c6 0e550 h 45 h +0f5 h =13a h ?
hms81c4x60 30 november 2001 ver 1.1 y indexed direct page (8 bit offset) ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h f100: d500fa lda !0fa00 h +y (6) indirect addressing direct page indirect ? [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 fa00: 3f35 jmp [35 h ] x indexed indirect ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h fa00: 1625 adc [25 h +x] d5 0f100 h data ? a t ~ ~ ~ ~ data 0fa55 h 0fa00 h +55 h =0fa55 h ? fa 0f102 h 00 0f101 h 0a 35 h jump to address 0e30a h t ~ ~ ~ ~ 35 0fa00 h e3 36 h 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ ? a + data + c ? a 25 + x(10) = 35 h t
hms81c4x60 november 2001 ver 1.1 31 y indexed indirect ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h fa00: 1725 adc [25 h ]+y absolute indirect ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 fa00: 1f25e0 jmp [!0e025 h ] 05 25 h 0e005 h + y(10) = 0e015 h t ~ ~ ~ ~ 25 0fa00 h e0 26 h 17 0e015 h data ~ ~ ~ ~ ? a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h 25 0e725 h next ~ ~ ~ ~ 1f program memory t address 0e725 h
hms81c4x60 32 november 2001 ver 1.1 9. i/o ports the hms81c4x60 has 5 ports (r0, r1, r2, r3 and r4) and osd ports (r,g,b,ys,ym). these ports pins may be multiplexed with an alternatefunction for the peripheral features on the device. in general, in an initial reset state, r ports are used as a general purpose digital port. 9.1 registers for port port data registers the port data registers (r0, r1, r2, r3, r4) are repre- sented as a d-type flip-flop, which will clock in a value from the internal bus in response to a write to data regis- ter signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a read data reg- ister signal from the cpu. the level of the port pin itself is placed on the internal bus in response to read data reg- ister signal from the cpu. some instructions that read a port activating the read register signal, and others acti- vating the read pin signal. port direction registers all pins have data direction registers which can define these ports as output or input. a 1 in the port direction register configure the corresponding port pin as output. conversely, write 0 to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write 55 h to address 0c1 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1. all the port direction registers in the hms81c4x60 have been written to zero by reset function. on the other hand, its initial status is input. figure 9-1 example of port i/o assignment i : input port write 55 h to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r4 data r0 direction r4 direction 0c0 h 0c1 h 0c8 h 0c9 h 76543210 bit 76543210 port o : output port ~ ~ ~ ~ 0 1 0 1 0 1 0 1 76543210 bit
hms81c4x60 november 2001 ver 1.1 33 9.2 i/o ports configuration r0 ports r07 ~ r04 is an open drain bidirectional i/o port and r03 ~ r00 is a cmos bidirectional i/o port(address 0c0 h ). each i/o pin can independently used as an input or an out- put through the r0dd register (address 0c1 h ). the control registers for r0 are shown below. r1 ports r1 is a 5-bit cmos input port only(address 0c2 h ). each pin can independently used as an input through the r1dd register (address 0c3 h ). user can use r0dd register when its bit is 0 only. the control registers for r1 are shown be- low. r1 port also can use the value bit5 ~ bit0 of aips register to secondary function register. r1 port have secondary functions as following table. port r1 is multiplexed with various special features.the control registers controls the selection of alternate func- tion. after reset, this value is 0, port may be used as nor- mal input port. the way to select alternate function such as comparator input will be shown in each peripheral section. in addition, r1 port is used as key scan function which op- erate with normal input port. input or output is configured automatically by each func- tion register (ksmr) regardless of r1dd. r2 port r2 is a 6-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an out- put through the r2dd register (address 00c5 h ).the con- trol registers for r2 are shown below. r2 port also use the value bit5 ~ bit1 of func register to secondary function register. r2 port have secondary func- r/w r03 r/w r02 r/w r04 r/w r06 r/w r05 r/w r07 r/w r01 r/w r00 address : 00c0 h reset value : undefined r0 data register r0 w w w w w w w w address : 00c1 h reset value : 0000 0000 b r0 direction register r0dd port direction 0: input 1: output r r13 r r12 r r14 r r r r r11 r r10 address : 00c2 h reset value : undefined r1 data register r1 w w w w - w - w - w w address : 00c3 h reset value : ---0 0000 b r1 direction register r1dd port direction 0 : use input only msb lsb wwwwww ww aips1 aips2 aips3 aips4 aips5 - - aips0 aips initial value: --00 0000 h address: 00ef h aips.5 ~ aips.0 0 : r0 port 1 : adc input port pin alternate function r10 r11 r12 r13 r14 an0 (a/d input 0) an1 (a/d input 1) an2 (a/d input 2) an3 (a/d input 3) an4 (a/d input 4) r/w r23 r/w r22 r/w r24 r/w r/w r25 r/w r/w r21 r/w r20 address : 00c4 h reset value : undefined r2 data register r2 w w w w - w w - w w address : 00c5 h reset value : 0000 0000 b r2 direction register r2dd port direction 0: input 1: output initial value: 0000 0000 b address: 00ce h msb lsb wwwwww ww in t 1s int2s int3s ec2s ec3s - -1 func func.5 ~ func.1 0 : r2 port 1 : int mode, ec mode user must set 1
hms81c4x60 34 november 2001 ver 1.1 tions as following table. r3 port r3 is a 8-bit cmos bidirectional output port (address 0c6 h ). each i/o pin can independently used as an input or an output through the r3dd register (address 0c7 h ). the control registers for r3 are shown below. r3 port also use the value bit7 ~ bit0 of pwmcr1 register to secondary function register. r3 port have secondary functions as following table. r4 port r4 is a 4-bit open drain and bidirectional i/o port (address 0c8 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0c9 h ). the control registers for r4 are shown below. r4 port also use the value bit7 ~ bit6 of iccr register to secondary function register. r4 port have secondary func- tions as following table. port pin alternate function r21 r22 r23 r24 r25 int1 (external interrupt 1) int2 (external interrupt 2) int3 (external interrupt 3) ec2 (event counter 2) ec3 (event counter 3) r30 r31 r32 r33 r34 r35 r36 r37 pwm0 (pulse width modulation 0) pwm1 (pulse width modulation 1) pwm2 (pulse width modulation 2) pwm3 (pulse width modulation 3) pwm4 (pulse width modulation 4) pwm5 (pulse width modulation 5 - 14bit) buz (buzzer output) tmr1 (timer interrup 1) r/w r33 r/w r32 r/w r34 r/w r36 r/w r35 r/w r37 r/w r31 r/w r30 address : 00c6 h reset value : undefined r3 data register r3 w w w w w w w w address : 00c7 h reset value : 0000 0000 b r3 direction register r3dd port direction 0: input 1: output initial value: 0000 0000 b address: 00ea h msb lsb pwmcr.7 ~ pwmcr.0 r/w r/w r/w r/w r/w r/w r/w en1 en2 en3 en4 en5 buz tmr1 en0 pwmcr1 0 : r3 port 1 : pwm, buz, tmr1 r/w r40 r41 r42 r43 scl0 (serial clock 0) sda0 (serial data 0) scl1 (serial clock 1) sda1 (serial data 1) r/w r43 r/w r42 r/w r/w r/w r/w r/w r41 r/w r40 address : 00c8 h reset value : undefined r4 data register r4 w w w - w - w - w - w w address : 00c9 h reset value : 0000 0000 b r4 direction register r4dd port direction 0: input 1: output initial value: 0000 0000 b address: 00db h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w ccr1 ccr2 ccr3 eso ackb bsel0 bsel1 ccr0 iccr iccr.7 ~ iccr.6 00 : r4 port 01 : scl0, sda0, r42, r43 10 : scl1, sda1, r40, r41 11 : scl0, sda0, scl1, sda1
hms81c4x60 november 2001 ver 1.1 35 10. clock generator as shown in figure 10-1, the clock generation circuit con- sist pll that generate multiplicated frequency of crystal clock, generation circuit which create cpu clock, pres- caler which generate input clock of basic interval timer and variable hardware clock, basic interval timer which is generate standard time, watch dog timer which is protect software overflow. see 12.1 basic interval timer on page for de- tails. 10.1 clock generation circuit the clock signal come from crystal oscillator or ceramic via xin and xout or from external clock via xin is supplied to clock pulse generator and prescaler. internal system clock for cpu is made by clock pulse generator, and several peripherial clock is divided by pres- caler. clock generation circuit of crystal oscillator or ceramic resonator is shown as below. osc circuit pll clock pulse generator prescaler (11) mux basic interval timer(8) watch dog timer(6) comparator wdtr wdtcl peripheral circuit wdtcl ifwdt to reset btcl ckctrl 6 8 070 5 6 6 7 circuit data slicer clock osd clock internal system clock enpck 012345 ifbit 11 internal data bus 8 056 (16mhz typical) wdton
hms81c4x60 36 november 2001 ver 1.1 figure 10-1 cristal oscillator or ceramic resonator figure 10-2 external clock 10.2 phase locked loop pll(phase locked loop) from osc 4mhz clock circuit generate internal system clock, timer clock(ps0), data slicer clock, osd clock, etc. figure 10-3 pll control register 10.3 prescaler prescaler consistor of 11-bit binary counter, and input clock which is supplied by oscillation circuit. frequency divided by prescaler is used as a source clock for periphe- rial hardwares. figure 10-4 prescaler xout xin cout cin gnd xout xin external clock open initial value: -000 0000 b address: 00cf h msb lsb pll clock frequency pll clock frequency test mode wwwwww ww pcf0 pcf1 pcf2 - - - -pllon pllc 0 : off pll 000 : 8mhz 001 : 12mhz 1 : on pll, in the case system clock supply osd circuit 010 : 16mhz(typical) 011 : 24mhz 100 : 32mhz ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 f ex enpck ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 peripheral b.i.t 12 8
hms81c4x60 november 2001 ver 1.1 37 peripheral clock supplied from prescaler can be stopped by enpck. peripheral clock is determined by ckctlr register.(however, ps11 cannot be stopped by enpck) figure 10-5 clock control register initial value: --00 0000 b address: 00f6 h msb lsb b.i.t input clock select b.i.t clear (when write) b.i.t value (when read) wwwwww ww bts1 bts2 btcl enpck wdton - -bts0 ckctlr 0 : b.i.t free-run 1 : b.i.t clear (auto reset when after 1 cycle) 000 : ps4 (4 m s) 001 : ps5 (8 m s) 010 : ps6 (16 m s) 011 : ps7 (32 m s) 100 : ps8 (64 m s) 101 : ps9 (128 m s) 110 : ps10 (256 m s) 111 : ps11 (512 m s) peripherial clock enable (when write) 0 : peripherial clock stop 1 : peripherial clock supply wdt function control(when write) 0 : 6 bit timer 1 : watch-dog timer data : 00h ~ ffh
hms81c4x60 38 november 2001 ver 1.1 11. interrupts the hms81c4x60 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh and irql, priority circuit and master enable flag ("i" flag of psw). 16 interrupt sources are provided. the configuration of interrupt circuit is shown in figure 11-2. below table shows the interrupt priority the external interrupts can be transition-activated (1-to-0 or 0-to-1 transition). when an external interrupt is generated, the flag that gen- erated it is cleared by the hardware when the service rou- tine is vectored to only if the interrupt was transition- activated. the timer/counter interrupts are generated by tnif(n=0~3), which is set by a match in their respective timer/counter register. the basic interval timer interrupt is generated by bitif which is set by a overflow in the timer register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), that is the interrupt enable reg- ister (ienh, ienl) and the interrupt request flags (in irqh,irql) except power-on reset and software brk in- terrupt. interrupt mode register it controls interrupt priority. it takes only one specified in- terrupt. of course, interrupts priority is fixed by h/w, but some- times user want to get specified interrupt even if higher priority interrupt was occured. higher priority interrupt is occured the next time. it contains 2bit data to enable priority selection and 4bit data to select specified interrupt. figure 11-1 interrupt mode register reset/interrupt symbol priority hardware reset reserved osd interrupt external interrupt 1 external interrupt 2 timer/counter 0 timer/counter 2 slicer interrupt vsync interrupt timer/counter 1 timer/counter 3 interrupt interval measure watchdog timer basic interval timer reserved i 2 c interrupt reset - osd int1 int2 timer 0 timer 2 slicer vsync timer 1 timer 3 intv(int3/4) wdt bit - i2c - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bit no. name value function 5,4 im1~0 00 01 1x mode 0: h/w priority mode 1: s/w priority interrupt is disabled, even if ie is set. 3~0 ip3~0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 - osd int1 int2 timer 0 timer 2 slicer vsync timer 1 timer 3 intv(int3/4) wdt bit - i2c not used table 11-1 bit function r/w ip3 r/w ip2 r/w m0 r/w r/w m1 r/w r/w ip1 r/w ip0 address : 00f3 h reset value : undefined interrupt mode register imod
hms81c4x60 november 2001 ver 1.1 39 figure 11-2 block diagram of interrupt t0 timer 0 int2 int1 int2 int1 ifosd osd - ienh [00f6 h ] interrupt enable irqh interrupt vector address generator internal bus line register (higher byte) to cpu interrupt master enable flag i flag priority control i-flag is in psw , it is cleared by "di", set by "ei" instruction. w hen it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is com pleted by "reti" instruction, i-flag is set to "1" by hardware. t2 timer 2 slice slicer vsync ifvsync wdt ifwdt ifbit bit - ifi2c i2c ienl [00f4 h ] irql intv intr. interval t3 timer 3 t1 timer 1 [00f5 h ] internal bus line imod [00f3 h ] bit5 interrupt enable register (lower byte) reset brk [0f7 h ]
hms81c4x60 40 november 2001 ver 1.1 interrupt request flag registers are shown in figure 11-3. interrupt request is generated when suitable bit is set, and suitable request flag of accepted interrup is clear when in- terrupt processing cycle. suitable bit is set when interrupt request is occured, but no accepted request flag is set to hold when the interrupt is accepted. also, interrupt request flag register(irqh, irql) is the register of read or write. so, request flag can be changed by program. figure 11-3 interrupt request flag registers int2 r/w - vsync interrupt request flag initial value: 0000 0000 b address: 00f7 h irqh osd msb lsb slice vsync t0 t2 int1 r/w r/w wdt r/w t1 initial value: 0000 000- b address: 00f5 h irql t3 msb i2c bit intv r/w r/w r/w - r/w r/w r/w r/w r/w r/w r/w r/w slicer interrupt request flag timer / counter 2 interrupt request flag timer / counter 0 interrupt request flag external interrupt 2 interrupt request flag external interrupt 1 interrupt request flag on screen display interrupt request flag i 2 c interrupt request flag lsb basic interval timer interrupt request flag watch-dog timer interrupt request flag interrupt interval measurement interrupt request flag (int3/4) timer / counter 3 interrupt request flag timer / counter 1 interrupt request flag -
hms81c4x60 november 2001 ver 1.1 41 interrupt enable flag registers are shown in figure 11-4. these registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. when enable flag is "0", a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which dis- ables all interrupts at once. figure 11-4 interrupt enable flag regesters int2 r/w - vsync interrupt enable flag initial value: 0000 0000 b address: 00f6 h ienh osd msb lsb slice vsync t0 t2 int1 r/w r/w wdt r/w t1 initial value: 0000 000- b address: 00f4 h ienl t3 msb i2c bit intv r/w r/w r/w - r/w r/w r/w r/w r/w r/w r/w r/w slicer interrupt enable flag timer / counter 2 interrupt enable flag timer / counter 0 interrupt enable flag external interrupt 2 interrupt enable flag external interrupt 1 interrupt enable flag on screen display interrupt enable flag i 2 c interrupt enable flag lsb basic interval timer interrupt enable flag watch-dog timer interrupt enable flag interrupt interval measurement interrupt enable flag (int3/4) timer / counter 3 interrupt enable flag timer / counter 1 interrupt enable flag -
hms81c4x60 42 november 2001 ver 1.1 11.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an in- struction. interrupt acceptance sequence requires 8 f ex (2 m s at f main =4mhz) after the completion of the current in- struction execution. the interrupt service task terminates upon execution of an interrupt return instruction [reti]. interrupt acceptance figure 11-5 interrupt service routine entering timing 1. the interrupt master enable flag (i-flag) is cleared to "0" to temporarily disable the acceptance of any fol- lowing maskable interrupts. when a non-maskable in- terrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to "0". 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decrements 3 times. 4. the entry address of the interrupt service program is read from the vector table address, and the entry ad- dress is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents.
hms81c4x60 november 2001 ver 1.1 43 a maskable interrupt is not accepted until the i-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. when nested interrupt service is necessary, the i-flag is set to "1" in the interrupt service program. in this case, accept- able interrupt sources are selectively enabled by the indi- vidual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other reg- isters. these registers are saved by the program if neces- sary. also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; 11.2 brk interrupt software interrupt can be invoked by brk instruction, which is the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 11-6. figure 11-6 execution of brk/tcall0 intxx: push a push x lda dpgr push a ;save acc. ;save x reg. ;save dpgr ; direct page ; accessable reg. ; : interrupt processing : pop a sta dpgr pop x pop a reti ;restore dpgr ;restore x reg. ;restore acc. ;return basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
hms81c4x60 44 november 2001 ver 1.1 11.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. figure 11-7 execution of multi interrupt however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user set i-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#20h ; enable int1 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#ffh ; enable all interrupts ldm ienl,#feh pop y pop x pop a reti enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
hms81c4x60 november 2001 ver 1.1 45 11.4 external interrupt the external interrupt on int1, int2... pins are edge trig- gered depending the edge selection register. refer to 6. port structures on page 12. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. figure 11-8 external interrupt block diagram int1, int2 and int3 are multiplexed with general i/o ports. to use external interrupt pin, the bit of port function register func1 should be set to "1" correspondingly. response time the int1, int2 and int3 edge are latched into int1if, int2if and int3if at every machine cycle. the values are not actually polled by the circuitry until the next ma- chine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. for example, the div instruction takes twelve machine cycles. thus, a minimum of twelve complete ma- chine cycles elapse between activation of an external inter- rupt request and the beginning of execution of the first instruction of the service routine figure 11-9 interrupt response timing diagram ( interrupt overhead ) int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt int3if int3 pin int3 interrupt ieds [00f2 h ] edge selection system clock instruction fetch last instruction execution (0~12cycle) enter interrupt service routine (8cycle) interrupt request sampling 1cycle interrupt overhaed (9~21cycle)
hms81c4x60 46 november 2001 ver 1.1 12. timer 12.1 basic interval timer the hms81c4x60 has one 8-bit basic interval timer that is free-run and can not be stopped. block diagram is shown in figure 12-1. the basic interval timer generates the time base for watchdog timer counting, and etc. it also provides a basic interval timer interrupt (bitif). as the count overflow from ff h to 00 h , this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 12-2. source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and ad- dress 00d6 h is read as a bitr and written to ckctlr.. figure 12-1 block diagram of basic interval timer figure 12-2 bitr basic interval timer mode register mux basic interval timer interrupt bitr select input clock 3 source clock 8-bit up-counter bitck btcl f ex ? 2 10 f ex ? 2 9 f ex ? 2 8 f ex ? 2 7 f ex ? 2 6 f ex ? 2 5 f ex ? 2 4 watchdog timer clock (wdtck) clear overflow internal bus line [0d6 h ] [0d6 h ] bitif clock control register ckctlr wdt enpck btcl bts2 bts1 bts0 on ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 f ex ? 2 11 initial value: undefined address: 00d6 h msb lsb rrrrrr rr bitr initial value: --00 0000 b address: 00d6 h msb lsb b.i.t clock b.i.t clear (when write) b.i.t value (when read) wwwwww ww bts1 bts2 btcl enpck wdton - -bts0 ckctlr 0 : b.i.t free-run 1 : b.i.t clear (auto reset when after 1 cycle) peripherial clock enable (write time) 0 : peripherial clock stop 1 : peripherial clock supply wdt function control 0 : 6 bit timer 1 : watch-dog timer caution : both register are in same address, when write, to be a ckctlr, when read, to be a bitr. 8-bit binary counter
hms81c4x60 november 2001 ver 1.1 47 12.2 timer 0, 1 timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, control register, and comparator as shown in figure 12-3 and figure 12-4. these timers can run separated 8bit timer or combined 16bit timer. these timers are operated by internal clock. the contents of tdr1 are compared with the contents of up-counter t1. if a match is found, a timer/counter 1 inter- rupt (t1if) is generated, and the counter is cleared. count- ing up is resumed after the counter is cleared. note: you can read timer 0, timer 1 value from tdr0 or tdr1. but if you write data to tdr0 or tdr1, it changes timer 0 or timer 1 modulo data, not timer value. the content of tdr0, tdr1 must be initialized (by soft- ware) with the value between 01 h and ff h ,not to 00 h . or not, timer 0 or timer 1 can not count up forever. the control registers for timer 0,1 are shown below. figure 12-3 timer / event count 0,1 (example) timer0 1ms time interval interrupt : : tdr_cnt: ldm tdr0,#249 ldm tdr1,#0 ldm tm0,#0011_1101b ; 4usec prescaler for t0 : : initial value: -000 0000 b address: 00d0 h msb lsb t0 input clock select(f ex =4mhz) timer 0 continue/hold control r/w r/w r/w r/w r/w r/w r/w r/w t0sl1 t0cn t0st t1sl0 t1sl1 t1st -t0sl0 tm0 00 : ps2(1 m s) 0 : count hold 1 : count countinue 01 : ps4(4 m s) 10 : ps6(16 m s) 11 : ps8(64 m s) timer 0 start control 0 : count hold 1 : count clear and start timer 1 input clock(f ex =4mhz) 00 : timer 0 overflow (16bit mode) 01 : ps2(1 m s) 10 : ps4(4 m s) 11 : ps6(16 m s) timer 1start/hold control 0 : count hold 0 : count clear and start msb lsb r/w r/w r/w r/w r/w r/w r/w r/w tdr0 initial value: undefined address: 00d2 h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w tdr1 initial value: undefined address: 00d3 h
hms81c4x60 48 november 2001 ver 1.1 . figure 12-4 simplified block diagram of 8bit timer0, 1 figure 12-5 count example of timer 8bit comparator internal bus line tm0 tdr0 timer 0 t0if clock tdr1 timer 1 clock clear clear 8bit comparator t1if mux ps2 ps4 ps6 ps8 mux nc ps2 ps4 ps6 t0cn t0st t1st timer 0 (t0if) interrupt tdr0 time occur interrupt occur interrupt stop clear & start disable enable start & stop t0st t0cn control count up-count ~ ~ ~ ~ t0st = 0 t0st = 1 t0cn = 0 t0cn = 1
hms81c4x60 november 2001 ver 1.1 49 figure 12-6 simplified block diagram of 16bit timer0, 1 internal bus line tm0 tdr0 timer 0 clock tdr1 timer 1 clock clear clear 16bit comparator t1if mux ps2 ps4 ps6 ps8 t0cn t0st 00
hms81c4x60 50 november 2001 ver 1.1 12.3 timer / event counter 2, 3 timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, control register, and comparator as shown in figure 12-7 and figure 12-8. these timers have two operating modes. one is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin r24/ec2, r25/ec3. these timers can run separated 8bit timer or combined 16bit timer. note: you can read timer 2, timer 3 value from tdr2 or tdr3. but if you write data to tdr2 or tdr3, it changes timer 2 or timer 3 modulo data, not timer value. the content of tdr2, tdr3 must be initialized (by soft- ware) with the value between 01 h and ff h ,not to 00 h . or not, timer 2 or timer 3 can not count up forever. the control registers for timer 2,3 are shown below figure 12-7 timer / event count 2,3 initial value: -000 0000 b address: 00d1 h msb lsb t2 input clock select timer 2 continue/hold control r/w r/w r/w r/w r/w r/w r/w r/w t3sl1 t3cn t3st t3sl0 t3sl1 t3st -t3sl0 tm2 00 : external event input(ec2) 0 : count hold 1 : count countinue 01 : ps2(1 m s) 10 : ps4(4 m s) 11 : ps6(16 m s) timer 2 start/hold control 0 : count hold 1 : count clear and start timer 3 input clock 00 : connected to t2(16bit mode) 01 : external event input(ec3) 10 : ps2 (1 m s) 11 : ps6 (16 m s) timer 3 start/hold control 0 : count hold 0 : count clear and start msb lsb r/w r/w r/w r/w r/w r/w r/w r/w tdr1 tdr2 tdr3 tdr4 tdr5 tdr6 tdr7 tdr0 tdr2 initial value: undefined address: 00d4 h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w tdr1 tdr2 tdr3 tdr4 tdr5 tdr6 tdr7 tdr0 tdr3 initial value: undefined address: 00d5 h initial value: 0000 000- b address: 00ce h msb lsb wwwwww ww int1s in t 2s in t 3s ec0s ec1s - -- func r24/ec2 select r25/ec3 select 0 : r24 1 : ec2 0 : r25 1 : ec3
hms81c4x60 november 2001 ver 1.1 51 . figure 12-8 simplified block diagram of 8bit timer/event counter 2,3 figure 12-9 count example of timer / event counter 8bit comparator internal bus line tm2 tdr2 timer 2 t2if clock tdr3 timer 3 clock clear clear 8bit comparator t3if mux ec2 ps2 ps4 ps6 mux nc ec3 ps2 ps4 t2cn t2st t3st timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt stop clear & start disable enable start & stop t2st t2cn control count up- co unt ~ ~ ~ ~ t2st = 0 t2st = 1 t2cn = 0 t2cn = 1
hms81c4x60 52 november 2001 ver 1.1 figure 12-10 simplified block diagram of 16bit timer/event counter 2,3 timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock in- put. the contents of tdrn (n=0~3) are compared with the contents of up-counter, timer n. if match is found, a timer n interrupt (tnif) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdrn is changeable by software, time in- terval is set as you want u figure 12-11 timer mode timing chart event counter mode in event timer mode, counting up is started by an external trigger. this trigger means falling edge of the ecn (n=0~1 ) pin input. source clock is used as an internal clock select- ed with tm2. the contents of tdrn are compared with the contents of the up-counter. if a match is found, an tnif in- terrupt is generated, and the counter is cleared to 00 h . the counter is restarted by the falling edge of the ecn pin in- put. the maximum frequency applied to the ecn pin is f ex /2 [hz] in main clock mode. in order to use event counter function, the bit ec0s, ec1s of the port function select register func(address 0ce h ) is required to be set to "1". after reset, the value of tdrn is undefined, it should be internal bus line tm2 tdr2 timer 2 clock tdr3 timer 3 clock clear clear 16bit comparator t3if mux ec2 ps4 ps6 ps8 t0cn t0st 00 0 n-2 2 0 n 3 n-1 n ~ ~ ~ ~ ~ ~ source clock up-counter tdrn (n=0~3) tnif (n=0~3) interrupt start count ~ ~ 12 3 ~ ~ ~ ~ 1 4 match detect counter clear
hms81c4x60 november 2001 ver 1.1 53 initialized to between 01 h ~ff h s not to 00 h u figure 12-12 event counter mode timing chart the interval period of timer is calculated as below equa- tion. figure 12-13 count example of timer / event counter 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ecn (n=2~3) pin up-counter tdrn (n=2~3) tnif (n=2~3) interrupt start count period 1 f ex ----- - prescaler ratio tdr n = ~ ~ timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt occur interrupt interrupt period up - coun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 n n-1 p cp = p cp x n n-2 tdr2=n
hms81c4x60 54 november 2001 ver 1.1 figure 12-14 count operation of timer / event counter timer 2 (t2if) interrupt tdr2 time occur interrupt occur interrupt stop clear & start disable enable start & stop t2st t2cn control count up- co unt ~ ~ ~ ~ t2st = 0 t2st = 1 t2cn = 0 t2cn = 1
hms81c4x60 november 2001 ver 1.1 55 13. a/d converter the a/d converter circuit is shown in figure 13-1. the a/d converter circuit consists of the comparator and control register aips(00ef h ), adcm(00f0 h ), adr(00f1 h ). the aips register select normal port or an- alog input. the adcm register control a/d converters activity. the adr register stores a/d converted 8bit re- sult. the more details are shown figure 13-2. figure 13-1 block diagram of a/d convertor circuit control the hms81c4x60 contains a a/d converter module which has six analog inputs. 1. first of all, you have to select analog input pin by set the adcm and aips. 2. set aden (a/d enable bit : adcm bit5). 3. set adst (a/d start bit : adcm bit1). we recommend you do not set aden and adst at once, it makes worse a/d converted result. 4. adst bit will be cleared 1 cycle automatically after you set this. [example] ;set aips, change ? to what you want ; 0 : digital port ; 1 : analog port ldm aips,#0000_1000b ; set aden, xxx is analog port number ldm adcm,#0010_1100b ; or set1 aden ; set adst, xxx is analog port number ldm adcm,#0010_11110b bbc adcm.adsf,$ lda adr ; or set1 adst : : 5. after a/d conversion is completed, adsf bit and inter- rupt flag ifa will be set. (a/d conversion takes 36 ma- chine cycle : 18us when f ex =4mhz). note: make sure aips bits, if you using a port which is set digital input by aips, analog voltage will be flow into mcu internal logic not a/d converter. sometimes device or port is damaged permanently. comparator an0 mux an1 an2 an3 port select + - s/h adcm [f0 h ] aden ads2 ads1 ads0 adst adsf adr [f1 h ] an4 control circuit register ladder succesive approximation circuit ifa vref 5 0 data bus 0 1 2 3 4 5 6 7 8 8 8
hms81c4x60 56 november 2001 ver 1.1 figure 13-2 a/d convertor registers figure 13-3 a/d conversion data register initial value: --01 1101 b address: 00f0 h msb lsb a/d converter status bit a/d converter start bit r/w r/w r/w r/w r/w r/w r/w r adst ads0 ads1 ads2 aden - -adsf adcm 0 : busy 0 : ignore 1 : a/d start (0 after 1 cycle) 1 : a/d conversion completed analog port select 000 : an0 select 001 : an1 select 010 : an2 select 011 : an3 select a/d converter enable bit 0 : disable 1 : enable 100 : an4 select 101 : default 110 : default 111 : default msb lsb rrrrrr rr tdr1 tdr2 tdr3 tdr4 tdr5 tdr6 tdr7 tdr0 adr initial value: undefined address: 00f1 h msb lsb wwwwww ww aips1 aips2 aips3 aips4 - - - aips0 aips initial value: ---0 0000 h address: 00ef h analog input select 0 : p1 input 1 : adc input ads2 ads1 ads0 function port select r14/an4 r13/an3 r12/an2 r11/an1 r10/an0 w 0 w an0 r14 r13 r12 r11 an0 w 0 x an1 r14 r13 r12 an1 r10 01 w an2 r14 r13 an2 r11 r10 0 1 x an3 r14 an3 r12 r11 r10 10 w an4 an4 r13r12r11r10
hms81c4x60 november 2001 ver 1.1 57 14. pulse width modulation (pwm) the pwm circuit is shown in figure 14-1, . the pwm circuit consists of the counter, comparator, data register. the pwm control registers are pwmr4~0, pwmcr2~1, pwm5h, pwm5l. the more details about registers are shown figure 14-2 . figure 14-1 8bit register (pwm7~0) circuit figure 14-2 14bit register (pwm8) circuit example (f ex =4mhz) 14bit pwm 8bit pwm resolution 14 bits 8 bits input clock 2mhz 250khz frame cycle 8,192us 1,024us pwmcr2 [eb h ] 8bit counter pwm0 pwmcr1 [ea h ] 8bit comparator pwmr0 [e0 h ] en5 en4 en3 en2 en1 en0 pwmr1 [e1 h ] pwmr2 [e2 h ] pwmr3 [e3 h ] pwmr4 [e4 h ] pwmr5 [e5 h ] pwm5 pwm4 pwm3 pwm2 pwm1 if1frame ps5 cntb cntb en5 en4 en3 en2 en1 en0 3 21 0 pwmcr2 [eb h ] 14bit counter pwm8 pwmcr1 [ea h ] 14bit comparator pwmr5h 8bit [e8 h ] en8 ps2 cntb pwmr5l 6bit [e9 h ] msb lsb internal control cnt
hms81c4x60 58 november 2001 ver 1.1 8bit pwm control the hms81c4x60 contains a one 14bit pwm and five 8bit pwm module. 1. 8bit pwm0~5 is wholy same internal circuit, but pwm0~5 output port is cmos bidirectional i/o pin. 2. al l pwm polarity has the same by pol2s value. 3. calulate frame cycle and pulse width is as following. pwm frame cycle = 2 13 / f ex (sec) pwm width = (pwmrn+1) 2 5 / f ex (n=0~5) pulse duty (%) = (pwmrn +1) / 256 100(%) (n=0~5) figure 14-3 wave form example for 8bit pwm 4. pwm output is enabled during enn(n=0~5) bit (see pwmcr1~2) contains 1. figure 14-4 8bit pwm registers 5. cntb controls all pwm counter enable. if cntb=0, than counter is disabled. 14bit pwm control 1. 14bit pwms operation concept is not the same as 8bit pwm. 1 pwm frame contains 64 sub pwms. pwm5h : set sub pwms basic pulse width. pwm5l : number of sub pwm which is added 1 clock. 2. pwm polarity is selected by pol1s value. if pol1=0, positive polarity. 3. calulate frame cycle and pulse width is as following. main pwm frame cycle = 2 16 / f ex (sec). sub pwm frame cycle = main frame cycle / 64. 4. table 14-1, pwm5l and sub frame matching table, on page 58 show pwm5l function. figure 14-5 wave form example for 14bit pwm figure 14-6 pwm5h, pwm5l register positive polarity (pol2=0) 1 2 negative polarity (pol2=1) 1 2 1. frame cycle 2. pulse width msb lsb r/w r/w r/w r/w r/w r/w r/w r/w pwm0d7 pwmr4~0 initial value: undefined address: 00e0 h ~e4 h pwm0d6 pwm0d5 pwm0d4 pwm0d3 pwm0d2 pwm0d1 pwm0d0 each pwm data store bit value sub frame number which is added 1 clock pulse count if bit0=1 32 1 if bit1=1 16, 48 2 if bit2=1 8, 24, 40, 56 4 if bit3=1 4, 12, 20, 28, 36, 44, 52, 60 8 if bit4=1 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 16 if bit5=1 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 32 table 14-1 pwm5l and sub frame matching table main pwm frame ..... 012 616263 sub pwm frame sub pwm frame which is added 1 clock 1 clock width : ps2 msb lsb r/w r/w r/w r/w r/w r/w r/w r/w pwm5h7 pwm5h initial value: undefined address: 00e8 h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w pwm5l initial value: undefined address: 00e9 h pwm5h6 pwm5h5 pwm5h4 pwm5h3 pwm5h2 pwm5h1 pwm5h0 pwm5l0 pwm5l1 pwm5l3 pwm5l4 pwm5l5 - - pwm5l2
hms81c4x60 november 2001 ver 1.1 59 figure 14-7 pwm control register 1 figure 14-8 pwm control register 2 initial value: 0000 0000 b address: 00ea h msb lsb r30/pwm0 select r31/pwm1 select r/w r/w r/w r/w r/w r/w r/w r/w en1 en2 en3 en4 en5 buz tmr1 en0 pwmcr1 0 : r30 0 : r31 1 : pwm1 1 : pwm0 r32/pwm2 select 0 : r32 1 : pwm2 r33/pwm3 select 0 : r33 1 : pwm3 r34/pwm4 select 0 : r34 1 : pwm4 r35/pwm5 select 0 : r35 1 : pwm5 r3 ] / buzzer select 0 : r36 1 : buzzer output r37/tmr1 select 0 : r37 1 : tmr1 initial value: 0000 0000 b address: 00eb h msb lsb 14bit/8bit pwm count stop/start 14bit pwm output polarity r/w r/w r/w r/w r/w r/w r/w r/w pol14 pol8 - - - - - cntb pwmcr2 0 : count start 0 : positive polarity 1 : negitive polarity 1 : count stop 8bit pwm output polarity 0 : positive polarity 1 : negative polarity
hms81c4x60 60 november 2001 ver 1.1 15. interrupt interval measurement circuit the interrupt interval measurement circuit is shown in fig- ure 15-1. the interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, edge detec- tor, 8bit counter, measured result storing register, fifo (9 bit, 6 level) interrupt, control register, etc. the more details about registers are shown figure 15-2 . figure 15-1 block diagram of interrupt interval measurement circuit control the hms81c4x60 contains a interrupt interval measure- ment module. 1. select interrupt input pin what you want to measure by set the func [00ce h ]. 2. set idcr [00f9 h ] : fifo clear, interrupt mode select, interrupt edge select, external interrupt int3 select, sam- pling clock select, count start/stop select. 3. set idcr [00f9 h ] : set idst to start measuring. 4. counter value is stored to idr [00fb h ] when selected edge is detected. after data was written, timer is cleard au- tomatically and it counts continue. 5 . you can select interrupt occuring point by set interrupt mode select bit (ims), every edge what you selected or fifo 4 level is filled. 6. if input signals interval is larger than maximum counter value (0ff h ), counter occurring an interrupt and count again from 00 h . 7. see figure 15-7 fifo operating mechanism. [example] ;set int3 for remote control pulse reception ldm func,#0000_1001b;int3 set ldm idcr,#1001_0001b ;64usec pcs : : mux idcr [f9 h ] i34h i34l isel idck idst idfs [fa h ] int3 8bit counter fifo (9bit, 6level) int34 ims 1 0 dpol foe fful femp fclr mux ps8 ps9 1 0 mux 0 1 edge detector clear idr [fb h ] d7 d6 d5 d4 d3 d2 d1 d0 overflow 8 4 fclr 7 data bus 4
hms81c4x60 november 2001 ver 1.1 61 figure 15-2 int. interval determination control register figure 15-3 port function select register figure 15-4 port function select register initial value: 0001 -000 b address: 00f9 h msb lsb counter control sample clock select r/w r/w r/w r/w r/w r/w r/w r/w idck isel - i34l i34h im s fclr idst idcr 0 : stop 0 : ps9(128usec) 1 : ps8(64usec) 1 : clear & count external interrupt select 0 : int3 fixed interrupt mode 0 : every selected edge by i34h/l 1 : every fifo 4level is filled external interrupt edge select 00 : no select 01 : falling edge 10 : rising edge 11 : both edge fifo clear 0 : ignored 1 : clear & return to 0 initial value: 0--- -001 b address: 00fa h msb lsb fifo empty flag fifo full flag r/w r/w r/w r/w r/w r/w r/w r/w fful foe dpol femp idfs 0 : data filled 0 : not full 1 : full 1 : empty fifo overrun error flag 0 : no error 1 : error detected data polarity 0 : data is stored every falling edge 1 : data is stored every rising edge initial value: --00 000- b address: 00ce h msb lsb wwwwww ww in t1s int2s int3s ec2s ec3s - -- func r24/int3 select 0 : r23 1 : int3
hms81c4x60 62 november 2001 ver 1.1 figure 15-5 setting for measurement figure 15-6 int. interval determination fifo data register figure 15-7 example for fifo operating mechanism item symbol i34h i34l detecting edge frame cycle c 1 0 rising edge d 01 falling edge pulse width e 1 1 both edge f 1 1 both edge c f d e interrupt input msb lsb rrrrrr rr d1 d2 d3 d4 d5 d6 d7 d0 idr initial value: undefined address: 00fb h 1) fifo storing mechanism 2) fifo reading mechanism femp=1, fful=0 femp=0, fful=0 femp=0, fful=0 femp=0, fful=1 femp=0, fful=1 femp=0 femp=0 femp=1 read out read out data in data in data in data in data 6 will be erased. data 1 data 1 data 2 data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 2 data 1 data 2 data 3 data 4 data 5 data 7 foe=1 (over run error)
hms81c4x60 november 2001 ver 1.1 63 16. buzzer driver the buzzer driver circuit is shown in figure 16-1. the buzzer driver circuit consists of the 6bit counter, 6bit comparator, buzzer data register bur(00ee h ). the bur register controls source clock and output frequency. the more details about registers are shown figure 16-2 . figure 16-1 block diagram of buzzer driver circuit control the hms81c4x60 contains a buzzer driver module. 1. select an input clock among ps7~ps10 by set the buck1~0 of bur. 2. select output frequency by change the bu5~0. output frequency = 1 / (psx buy 2) hz. x=7~10, y=5~0 see example table 16-1. note: do not select 00 h to bu5~0. it means counter stop. 3. set buz bit for output enable. 4. output waveform is rectagle clock which has 50% duty. 5. you can use this clock for the other purposes. figure 16-2 buzzer driver registers bur [ee h ] bu5 bu4 bu3 bu2 bu1 bu0 6bit counter output generator buzz buck mux ps7 ps9 ps8 ps10 buck 10 00 01 10 11 clear 6bit comparator clear bur write 6 6 data bus 8 pwmcr1 tmr1 buz en5 en4 en3 en2 en1 en0 buck1 buck0 clock source 0 0 ps7 0 1 ps8 1 0 ps9 1 1 ps10 buzzer data register bur address : 0ee h reset value : ???? ???? b input select buzzer count data pwm control register 1 pwmcr1 address : 0ea h reset value : 0000 0000 b r36/buzz select 0: r36 1: buzz output w www wwww rw rw rw tmr1 buz en5 en4 en3 en2 en1 en0 buck1 buck0 bu5 bu1 bu2 bu3 bu4 bu0 rw rw rw rw rw
hms81c4x60 64 november 2001 ver 1.1 bur5~0 output frequency (khz) dec hex ps7 (32 m s) ps8 (64 m s) ps9 (128 m s) ps10 (256 m s) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 62.50 31.25 20.872 15.626 12.50 10.416 8.928 8.814 6.942 6.25 5.682 5.208 4.808 4.484 4.166 3.906 3.676 3.472 3.288 3.124 2.876 2.840 2.718 2.604 2.50 2.404 2.316 2.232 2.156 2.084 2.016 1.952 1.894 1.838 1.786 1.736 1.690 1.644 1.602 1.562 1.524 1.488 1.454 1.420 1.388 1.358 1.33 1.302 1.276 1.25 1.226 1.202 1.18 1.158 1.136 1.116 1.096 1.078 1.06 1.042 1.024 1.008 0.992 125.0 62.5 41.744 31.252 25.0 20.832 17.858 17.628 13.884 12.5 12.364 10.416 9.616 8.968 8.332 7.812 7.342 6.944 6.576 6.248 5.752 5.680 5.436 5.208 5.0 4.808 4.632 4.464 4.302 4.168 4.032 3.904 3.788 3.676 3.552 3.472 3.380 3.288 3.204 3.124 3.048 2.978 2.908 2.840 2.776 2.706 2.66 2.604 2.542 2.5 2.452 2.404 2.36 2.316 2.272 2.232 2.192 2.156 2.12 2.084 2.048 2.016 1.984 250.0 125.0 83.488 62.504 50.0 41.664 35.716 35.256 27.768 25.0 24.728 20.832 19.232 17.936 16.664 15.624 14.684 13.888 13.152 12.496 11.504 11.360 10.872 10.416 10.0 9.616 9.262 8.928 8.604 8.336 8.064 7.808 7.576 7.352 7.104 6.944 6.760 6.576 6.408 6.248 6.096 5.956 5.816 5.680 5.552 5.412 5.320 5.208 5.184 5.0 4.904 4.808 4.720 4.632 4.544 4.464 4.384 4.312 4.24 4.168 4.096 4.032 3.968 table 16-1 . example for f ex =4mhz
hms81c4x60 november 2001 ver 1.1 65 17. on screen display (osd) the hms81c4x60 can support 512 osd chacters and font size is used 12 10, 1212, 1214, 1216, 1618 . it can support 48 character columns and 2 line buffers respective- ly and also support full screen osd when use interrupt. each characters have bit plane of 24bit and support at- tribute with osd line and full screen osd respectively. osd circuit consists of the position attribute register, line register, full screen screen control register, i/o polarity register, font rom, vram, etc. on screen display block diagram is shown in figure 17-1 and the more details about display characters are shown in figure 17-2. figure 17-1 block diagram of on screen display circuit l1attr [af0 h ] osd control circuit osdln [ae5 h ] osdcon1 [ae0 h ] osdcon2 [ae1 h ] line 1,2 attribute, position register line register full screen control display on/off control register l1vpos [af1 h ] l2attr [af3 h ] l2vpos [af4 h ] lhpos [ae6 h ] horizontal position register vram font rom dac color pallet osd generation circuit output control circuit synchronization circuit hsync vsync r g b ys ym dot clock xin pll fdwset [ae3 h ] field detection register edgecol [ae4 h ] edge color register osdcon3 [ae2 h ] i/o porarity rigister register
hms81c4x60 66 november 2001 ver 1.1 figure 17-2 osd character font example [12 10 character font] [12 12 character font] [12 14 character font] [12 16 character font] [16 18 character font] osd background shadow foreground character - 512 color (8 pallet) - color selecting : vram n-character bit 19~16 background - 512 color (8 pallet) - color selecting : vram n-character bit 23~20 foreground character outline - setting by lnattr register - color selecting : edgecol register character shadow - setting by lnattr register and vram n-character bit 9 - color selecting : edgecol register background shadow color - setting by vram n-character bit 15~12 - color selecting : edgecol register - 512 color (8 pallet) - character flash - background underline - italic (only 12 12 mode can be supported)
hms81c4x60 november 2001 ver 1.1 67 17.1 feature of osd the feature of osd shown in below. - font pixel matrix : 12 10, 1212, 1214, 1216, 1618 dots - the number of font pattern : 512 fonts - display ability : 48character n lines (multilined by osd interrupt) - 8 foreground pallet of 512 colors for each character - 8 background pallet of 512 colors for each character - full screen 8 background color - character size : 3 fonts(2 times, 1.5 times, 1 times) - progressive scan line switch - attribute : outline, shadow, rounding - rgb dac : 8 level each color - display clock frequency : 12mhz ~ 64mhz 17.2 osd registers figure 17-3 osd control registers - 1 osdcon1 bit 0: stock it stop or start osd clock. if oscillation is stoped, ics power consumption is decreased. bit 1: ddclk if you set this bit to 1, osd input clock is divided by two , than it makes osd horisontal image size as doubled. bit 2: dline if you set this bit to 1, osd vertical scan counter input clock is doubled from normal state. it makes osd vertical initial value: 0000 0000 b address: 0ae0 h msb lsb stop osd clock double dot clock mode r/w r/w r/w r/w r/w r/w r/w r/w ddclk dline prscn fsbc0 fsbc1 fsbc2 fsbc3 stock osdcon1 0 :release osd clock 0 : normal 1 : double 1 : stop osd clock double scan line mode 0 : normal 1 : double progressive scan line mode 0 : interace mode 1 : progressive mode full screen background color register 0000 : transparency 0001 : half blank 0010 : white 0011 : black 0111 ~ 0100 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7
hms81c4x60 68 november 2001 ver 1.1 image size as doubled. bit 3: prscn it control progressive scan line mode. bit clear than interace mode and bit set than processive mode. bit 7~4: fsbc3 ~ fsbc0 it controls full screen background color as figure shows. note: data slicer operate when osdcon1.prscn(0ae0.3) bit of osd register is cleared. namely, it operate interace scan display mode. figure 17-4 osd control register - 2 osdcon2 bit 0: osdon it controls osd, full screen background at once. it does not affect anything to vsync interrupt and osd interrupt, etc. bit 1: onl it controls osd line1 and line2 on/off. if its value is 1, osd line is on. bit 2 ~ 5: fs0 ~ fs3 it controls osd font size. bit 6: obgw it controls dot background width. default width is 12dots. if its value is set, 2 dots (background color) are added both left and right side of character. bit 7: flrat it controls osd flash rate when closed caption decoder is used. bit clear than 32 vsync is one period and bit set than 64 vsync is one period. initial value: 0000 0000 b address: 0ae1 h msb lsb on/off of all osd on osd line1 and line2 r/w r/w r/w r/w r/w r/w r/w r/w oln fs0 fs1 fs2 fs3 obgw flart osdon osdcon2 0 :off 0 : off osd line 1 : on osd line 1 : on font size 12/14 dot background width of 1 osd character 0 : 12 dot 1 : 14 dot flash rate when closed caption decoder is used 0 : 32 vsync is one period 1 : 64 vsync is one period 0000 : 12 16 0001 : 12 14 0010 : 12 12 0011 : 12 10 0111 ~ 0100 : reseved 1000 : 16 18 1111 ~ 1001 : reserved
hms81c4x60 november 2001 ver 1.1 69 figure 17-5 i/o polarity(initial) register osdcon3 bit7~0 : selck1, selck0, ondac, polrg, polym, polys, polhs, polvs it controls hsync/vsync polarity, ys/ym polarity, rgb polarity, rgb dac on/off and select dot clock. fdwset fdwset (field detection window setting) register de- tects the begin of vsync(vertical sync.) signal and distin- guishs its current field is even field or odd field. the region of fmin[2:0] ~ fmax[3:0] is field detection window. fmax[3:0] can divide the region between hsync(hori- zontal sync.) by 16 windows. you can assume there is 4 bit horizontal counter, for example hcount[3:0](hptr[10 :7]) which count 0~15. initial value: 0000 0000 b address: 0ae2 h msb lsb vsync polarity hsync polarity wwwwww ww selck1 osdcon3 0 : active low 0 : active low 1 : active high 1 : active high ys polarity rgb pin polarity 0 : active low 1 : active high on/off of rgb dac 0 : off 1 : on 0 : active low 1 : active high ym polarity 0 : active low 1 : active high select dot clock 00 : clock from dll 01 : clock from lc osc for eva only 10 : clock 1 for test 11 : reserved polhs polvs polys polym polrg ondac selck2 initial value: 0111 1010 b address: 0ae3 h msb lsb field detection min. pointer field detection polarity wwwwww ww fmin1 fmin2 dbflg fmax0 fmax1 fmax2 fmax3 fmin0 fdwset 0 : masking between min. and max. 1 : detect between min. and max. field detection max. pointer field detection window: ( {1b0, (fmin2 ~ fmin0)} < hptr[10:7] < (fmax3 ~ fmax0))
hms81c4x60 70 november 2001 ver 1.1 figure 17-6 fdwset detection region if the start of vsync is detected at the window, next field is even. else if vsync is detected another region of the win- dow, next field is odd. it means start of vsync is detected during fmin[2:0] < hcount[3:0] < fmax[3:0] and dbflg value is 0, it distinguish odd field. and, start of vsync is detected during fmin[2:0] < hcount[3:0] < fmax[3:0] and dbflg value is 1, it distinguish even field. fmin[2:0], fmax[3:0] are compared with the horizontal counter in osd block. figure 17-7 character, window color register edgecol bit 7 ~ bit 0 : edg1c0,edg1c1,edg1c2,edg1c3 edg2c0,edg2c1,edg2c2,edg2c3 it control shadow color, outline color and edge color. low 4 bits controls edge 1 shadow, outline color and high 4 bits controls edge 2 shadow, outline color. hsync ex1: vsync(odd) ex2: vsync(even) fmin fmax initial value: 1000 0111 b address: 0ae4 h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w edg2c3 edgecol edge 2 color of shadow, outline, edge edge 1 color of shadow, outline, edge 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0100 : same as foreground character color 0111 ~ 0101 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0100 : same as foreground character color 0111 ~ 0101 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 edg2c2 edg2c1 edg2c0 edg1c3 edg1c2 edg1c1 edg1c0
hms81c4x60 november 2001 ver 1.1 71 figure 17-8 scroll window color register chedcl bit 7 ~ bit 0 : shec0,shec1,shec2,shec3 winc0,winc1,winc2,winc3 it controls foreground shadow and outline edge color and scroll window background color. low 4 bits controls scroll window background color and high 4 bits controls foreground shadow outline edge color. figure 17-9 osd line register osdln bit 4 ~ bit 0 : vlr4 ~ vlr0 it shows current display osd line from 1 to 31. initial value: undefined address: 0ae5 h msb lsb wwwwww ww shec1 shec2 shec3 winc0 winc1 winc2 winc3 shec0 chedcl scroll window background color foreground shadow, outline edge color 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0100 : same as foreground character color 0111 ~ 0101 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0111 ~ 0100 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 initial value: ---0 0000 h address: 0ae6 h msb lsb rrrrrr rr vlr1 vlr2 vlr3 vlr4 - - -vlr0 osdln osd line being displayed 00000 : not displayed any osd line yet after vsync 00001 : 1st line osd being displayed ....... ....... 11111 : 31st line osd being displayed msb lsb wwwwww ww lh1 lh2 lh3 lh4 lh5 lh6 lh7 lh0 lhpos initial value: undefined address: 0ae7 h osd line horizontal position 00 h ~ ff h
hms81c4x60 72 november 2001 ver 1.1 figure 17-10 osd line horizontal position register lhpos bit 7 ~ bit 0 : lh7 ~ lh0 it control osd line horizontal position. position value from 00h to ffh. figure 17-11 dll mode register dllmod bit 2 ~ 0 : if you set this bit to 1, the status is changed test mode. bit 7 ~ bit 3 : dckf4 ~ dckf0 it control dot clock frequency. dot clock frequency is as below. table 17-1 dot clock frequency (f ex =4mhz) initial value: 0000 0000 h address: 0ae8 h msb lsb wwwwww ww - - dckf0 dckf1 dckf2 dckf3 dckf4 - dllmod 1 : osd test mode 1 : dll test mode 1 : reset clock count test mode dot clock frequency initial value: --00 0000 h address: 0ae9 h msb lsb rrrrrr rr - - - - - - -- dlltst value frequency dckf4 dckf4 dckf4 dckf4 dckf4 0 0 0 0 0 stop dll clock 00001 reserved 00010 reserved 0001164.00mhz 0010051.20mhz 0010142.67mhz 0011036.57mhz 0011132.00mhz 0100028.44mhz 0100125.60mhz 0101023.27mhz 0101121.33mhz 0110019.69mhz 0110118.29mhz 0111017.07mhz 0111116.00mhz 1000015.05mhz 1000114.22mhz 1001013.47mhz 1001112.80mhz 1010012.19mhz 1010111.63mhz 1011011.13mhz 1011110.67mhz 11000 reserved 11001 reserved value frequency dckf4 dckf4 dckf4 dckf4 dckf4
hms81c4x60 november 2001 ver 1.1 73 figure 17-12 osd line 1 attribute register l1attr bit 0 : l1v8 it is equivalent to l1vposs most significant bit(bit 8). see more details in l1vpos. bit 1: fsc1 it selects character outline and shadow color. if it is 1, it se- lect edge2 color of edgecol register. or not, it select edge1 color. according to edgecol register and this bit character and shadow colors are selected simulteneous- ly bit 3~2: csz11~csz10 it controls osd characters size ( normal, 1.5 times, 2 times). you can use this register and ddclk, dline bit, horizontal / vertical size can be controlled (x1, x1.5, x2). bit 4: ensh1 it enables line 1s character(foreground) shadow. bit 5: enol1 it enables line 1s character(foreground) outline. bit 6: wdsl1 it shows thickness of line 1s shadow and outline.this bit is set than one dot and bit clear is proportional to character size. if only character size is 2 times, 2 times per vertically and horizontally. in case 1 dot width would be enable. bit 7: obgh1 it controls characters background height. default height is 16dots. if its value is set, 2 dots (background color) are added both top and bottom side of character. initial value: 0000 0000 h address: 0aea h msb lsb wwwwww ww fsc1 csz10 csz11 ensh1 enol1 wdsl1 obgh1 l1v8 l1attr osd line 1 vertical position (bit 8) size of character enable/disable of shadow 00 : normal 01 : 1.5 times 10 : 2 times 11 : reserved 0 : disable 1 : enable enable/disable of outline 0 : disable 1 : enable width of shadow, outline 0 : 1 dot 1 : proportional to character size osd chraracter background height 0 : font height 1 : font height + 2 foreground shadow or outline color select 0 : edge 1 color 1 : edge 2 color
hms81c4x60 74 november 2001 ver 1.1 l1eatr it shows osd line 1 extend attribute register. l1vpos it shows osd line 1s vertical position in 9bit format (liv8 + l1vpos, 000 ~ 1ff h ). l2attr it shows osd line 2s attributes. its function is the same as l1attr. l2eatr it shows osd line 2s extened attribute register. l2vpos it shows osd line 2s vertical position. its function is the same as l1vpos. initial value: undefined address: 0aeb h msb lsb wwwwww ww sel1it sel1fl sel1ow sel1ul - - -sel1sh l1eatr select shadow/round of line 1 each character when select italic/upper edge of line 1 each character. select flash/left edge of line 1 character when select osd/window when display. if this bit is 0, select underline /lower edge of line 1 each character 0 : underline 1 : lower edge line vram.enrnd is set. 0 : round character 1 : shadow character italic character can be displayed only when character size is 1, 1.5 times, and vram.bsu is set. 0 : upper edge character 1 : italic character vram.bsl is set. 0 : left edge character 1 : flash background window would be displayed. 0 : background window selected 1 : osd line selected msb lsb wwwwww ww liv1 liv2 liv3 liv4 liv5 liv6 liv7 liv0 l1vpos initial value: undefined address: 0aec h osd line 1 vertical position 000 h ~ 1ff h msb lsb wwwwww ww fsc2 csz21 csz22 ensh2 enol2 wdsl2 obgh2 l2v2 l2attr initial value: undefined address: 0aed h msb lsb wwwwww ww sel2it sel2fl sel2ow sel2ul - - - sel2sh l2eatr initial value: undefined address: 0aee h msb lsb wwwwww ww l2v1 l2v2 l2v3 l2v4 l2v5 l2v6 l2v7 l2v0 l2vpos initial value: undefined address: 0aef h
hms81c4x60 november 2001 ver 1.1 75 winsh it shows osd scroll window start horizontal position. winsy it shows osd scroll window start vertical position. wineh it shows osd scroll window end horizontal position. winey it shows osd scroll window end vertical position. vcnt it shows vsync count register and counted by pixel clock. vcnt counter clock start at vsync start edge. hcnt it shows hsync count register and counted by pixel clock. hcnt counter clock start at hsync start edge. cultad it shows normal and test mode and 1.5 times mode. msb lsb wwwwww ww winsh7 winsh initial value: undefined address: 0af0 h osd scroll window start horizontal position winsh6 winsh5 winsh4 winsh3 winsh2 winsh1 winsh0 msb lsb wwwwww ww winsy7 winsy initial value: undefined address: 0af1 h osd scroll window start vertical position winsy6 winsy5 winsy4 winsy3 winsy2 winsy1 winsy0 msb lsb wwwwww ww wineh7 wineh initial value: undefined address: 0af2 h osd scroll window end horizontal position wineh6 wineh5 wineh4 wineh3 wineh2 wineh1 wineh0 msb lsb wwwwww ww winey7 winey initial value: undefined address: 0af3 h osd scroll window end vertical position winey6 winey5 winey4 winey3 winey2 winey1 winey0 msb lsb rrrrrr rr vcnt6 vcnt6 vcnt6 vcnt6 vcnt6 vcnt6 vcnt6 fldid vcnt initial value: undefined address: 0af4 h current scan line line vertical position [6:0] current display field 0 : odd field 1 : even field msb lsb rrrrrr rr hcnt1 hcnt2 hcnt3 hcnt4 hcnt5 hcnt6 hcnt7 hcnt0 hcnt initial value: undefined address: 0af5 h horizontal counter hptr[10:3] msb lsb wwwwww ww fil15 - - - - - -- cultad initial value: undefined address: 0af9 h 1.5 times character mode 0 : line double mode 1.5 times 1 : field interleaving mode 1.5 times normal/test mode select 00 : normal mode 01 ~ 11 : test mode
hms81c4x60 76 november 2001 ver 1.1 17.3 vram vram contains a osd line buffer, 48 characters at- tributes. each characters attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, char- acter and character number ( 000 h ~ 1ff h , 512 characters ), etc. table 17-3 vram attribute line no. character add. no. address (bit 47~0) hexa decimal 1 1a80a40a00 2a81a41a01 3a82a42a02 :::: 46 aad a6d a2d 47 aae a6e a2e 48 aaf a6f a2f 2 1b80b40b00 2b81b41b01 3b82b42b02 :::: 46 bad b6d b2d 47 bae b6e b2e 48 baf b6f b2f table 17-2 vram memory map bit no. name function 00~08 cg8 ~cg0 character font code 1ffh ~ 000h 09 enrnd round enable/disable 0 : disable 1 : enable 0a bscul edge color of upper and left background shadow edge 0 : edge 1 color 1 : edge 2 color 0b bscdr edge color of lower and right background shadow edge 0 : edge 1 color 1 : edge 2 color 0c bsu background shadow upper eddge control/italic depend on lxeatr.selxit 0 : disable 1 : enable if(lxeatr.selxit == 0) background shadow upper edge enable else(lxeatr.selxit == 1) italic enable 0d bsd background shadow lower edge control/underline depend on lxeatr.selxul 0 : disable 1 : enable if(lxeatr.selxul == 0) background shadow lower edge enable else(lxeatr.selxul == 1)underline enable 0e bsl background shadoww left edge control/flash(blinking) depend on lxeatr.selxfl 0 : disable 1 : enable if(lxeatr.selxfl == 0) background shadow left edge enable else(lxeatr.selxfl == 1) flash(flicking) enable 0f bsr background shadow right edge control 0 : disable 1 : enable 10~13 fc3 ~fc0 foreground color for character (11 colors) 14~17 bc3 ~bc0 background color for character (12 colors) bit no. name function
hms81c4x60 november 2001 ver 1.1 77 0a80 0a40 0a00 0a81 0a41 0a01 0a82 0a42 0a02 : : : 0aaf 0a6f 0a2f line 1 (page a) character 1 attr. character 2 attr. character 3 attr. 0b80 0b40 0b00 0b81 0b41 0b01 0b82 0b42 0b02 : : : 0baf 0b6f 0b2f line 2 (page b) character 1 attr. character 2 attr. character 3 attr. character 48 attr. character 48 attr. enrnd bscul bscdr bsu bsd bsl bsr cg8 cg1 cg2 cg3 cg4 cg5 cg6 cg7 cg0 reset value: undefined composition of vram character font address (512 fonts) cg8 see table 17-3 vram attribute fc1 fc2 fc3 bc0 bc1 bc2 bc3 fc0 character color select (11 characters) 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0111 ~ 0100 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 background color select (12 characters) 0000 : transparency 0001 : reserved 0010 : white 0011 : black 0111 ~ 0100 : reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7
hms81c4x60 78 november 2001 ver 1.1 17.4 character rom the hms81c4x60 character rom are used 512 types of font dot pattern data. as displayed one character, need 12 10 ~ 16 18bits dot pattern data. 1. each horizontal data (12dots) needs 2bytes rom. 2. one character is constructed with 16 horizontal data to vertically. as a result, one character needs 32bytes (2 16 bytes). 3. hms81c4x60 contains 512 characters. total font rom memory size is calculated as 16,384bytes ( 32bytes / character 512 characters ) 4. font rom memory is located from 10000 h ~ 17fff h , this memory can not be accessed by user program. 5. a characters address and dot position in font rom is described in figure 17-13. figure 17-13 character dot pattern charact er code address range upper 8bit lower 8bit 000 h 14000 h ~ 14011 h 10000 h ~ 10011 h 001 h 14020 h ~ 14031 h 10020 h ~ 10031 h 002 h 14040 h ~ 14051 h 10040 h ~ 10051 h :: : xyz h (14000h + xyz0h) ~ (14000h + 2*xyzfh) (10000h + xyz0h) ~ (10000h + 2*xyzfh) :: : 1fd h 17fa0 h ~ 17fb1 h 13fa0 h ~ 13fd1 h 1fe h 17fc0 h ~ 17fd1 h 13fc0 h ~ 13fd1 h 1ff h 17fe0 h ~ 17ff1 h 13fe0 h ~ 13ff1 h table 17-4 font rom memory map right address 14060 14061 left address 14062 14063 14064 14065 14066 14067 14068 14069 1406a 1406b 1406c 1406d 1406e 1406f 14070 14071 14072 14073 14074 14075 14076 14077 14078 14079 1407a 1407b 1407c 1407d 1407e 1407f 10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 1006a 1006b 1006c 1006d 1006e 1006f 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 1007a 1007b 1007c 1007d 1007e 1007f 12 14 16 18
hms81c4x60 november 2001 ver 1.1 79 17.5 color look up table figure 17-14 color look up table [example] color data table color_example_table: db 0000_0000b ;color 0 = gray db 0000_0011b ;color 1 = red db 0010_1011b ;color 2 = green ; db 0000_0000b ;color 3 = yellow db 0000_0101b ;color 4 = blue db 0100_1101b ;color 5 = magenta ; db 0000_0000b ;color 6 = cyan db 1001_0001b ;color 7 = half blue db 1111_0001b <0ad0 h > red0 <0ad1 h > red1 <0ad2 h > red2 <0ad3 h > green0 <0ad4 h > green1 <0ad5 h > green2 <0ad6 h > blue0 <0ad7 h > blue1 <0ad8 h > blue2 w wwww www 7 6543 210 b72 b62 b52 b42 b32 b22 b12 b02 r07 r60 r50 r40 r30 r20 r10 r00 r71 r62 r51 r41 r31 r21 r11 r01 r72 r62 r52 r42 r32 r22 r12 r02 g70 g60 g50 g40 g30 g20 g10 g00 g71 g61 g51 g41 g31 g21 g11 g01 g72 g62 g52 g42 g32 g22 g12 g02 b70 b60 b50 b40 b30 b20 b10 b00 b71 b61 b51 b41 b31 b21 b11 b01 composition of color 3 red : {r02,r01,r00} green : {g02,g01,g00} blue : {b02,b01,b00} composition of color 2 composition of color 1 composition of color 0 composition of color 4 composition of color 5 composition of color 6 composition of color 7 reset value : undefined
hms81c4x60 80 november 2001 ver 1.1 18. data slicer hms81c4x60 supports closed caption decoding standard with 0.5mhz data rate. also it can capture 4 horizontal lines information per frame, because it has 4 horozontal lines capture memory. it is able to select even or odd field at one field interval. data slicer captures caption informa- tion from line 21 in vertical blanking interval of cvbs, and stores these data to buffer memory. 18.1 data slicer circuit figure 18-1 shown the data slicer circuit. figure 18-1 data slicer circuit cvbs signal is entered to cvbs pin via 0.47uf capacitor. the black level of signal is about 2v. scap pin is connect- ed to external 560pf capacitor which adjust the referance voltage of comparator. its slicer level is adapted to input signal. 18.2 configuration of data slicer figure 18-2 shows the block diagram of the data slicer. figure 18-2 data slicer block diagram this data slicer block separates caption information from cvbs signal. data slicer composes high speed comparator and on-chip low pass filter. the output data of comparator is stored in memory through the filter and memory inter- face controller, which should be decoded to caption data by software. slicer memory addressed 600h ~ 6ffh. scap cvbs 560pf 0.47uf hms81c4x60 run-in key timing sync-tip timing data capture timing data filter memory interface controller slicer memory reference voltage cvbs timing controller cpu control
hms81c4x60 november 2001 ver 1.1 81 18.3 slicer registers slicer control register slicer control register is the specific control register, which select operating frequency of the slicer, slicer de- coding method and switch slicer on/off. figure 18-3 slicer control register slicer information register 0 slicer information register 0 selects even or odd field buffer of line 0 and slicer line 0 position. also it is used to select line number in vertical blanking interval. figure 18-4 slicer information register 0 slicer information register 1 slicer information register 1 selects even or odd field buffer of line 1 and slicer line 1 position. also it is used to select line number in vertical blanking interval. figure 18-5 slicer information register 1 initial value: 0000 0000 b address: 0be0 h msb lsb r/w r/w r/w r/w r/w r/w r/w r/w deme0 deme1 - - selck riktst -slon slcon slicer on/off decoding method slicer clock rik slicer test mode 0 : slicer off 1 : slicer on 00 : normal 01 : reserved 10 : reserved 11 : reversed 0 : normal clock 1 : test clock 00 : normal clock 01 : reserved 10 : reserved 11 : reserved initial value: 0000 0000 b address: 0be1 h msb lsb wwwwww ww lfc0 lfc0 slinf0 line0 enable slicer line 0 position 00 : disable all line 0 01 : reserved slpos0 10 : reserved 11 : enable all line 0 (even and odd field) initial value: 0000 0000 b address: 0be2 h msb lsb wwwwww ww lfc1 lfc1 slinf1 line 1 field slicer line 1 position 00 : disable all line 1 01 : reserved slpos1 10 : reserved 11 : enable all line 1 (even and odd field)
hms81c4x60 82 november 2001 ver 1.1 run-in key start/end position register rikst points the start postion of run-in key, it is delayed from start edge of hsync. riked points the end position of run-in key, it is also delayed from start edge of hsync. both timmings are counted up by 8mhz clock. the refer- ance voltage of comparator is charged by external signal during this time interval. figure 18-6 and figure 18-7 shows the rik registers configure. figure 18-6 run-in key start position register figure 18-7 run-in key end position register sync start/end position register sync start and end position register are used to make sync tip window. both timmings are counted up by 16mhz clock. figure 18-8 and figure 18-9 shows the sync-tip registers configure. figure 18-8 sync-tip start position register figure 18-9 sync-tip end position register initial value: xxxx xxxx b address: 0be3 h msb lsb wwwwww ww rikst1 rikst2 rikst3 rikst4 rikst5 rikst6 rikst7 rikst0 rikst run-in key window start position initial value: xxxx xxxx b address: 0be4 h msb lsb wwwwww ww riked1 riked2 riked3 riked4 riked5 riked6 riked7 riked0 riked run-in key window end position initial value: xxxx xxxx b address: 0be7 h msb lsb wwwwww ww sncst sync-tip window start position sncst7 sncst6 sncst5 sncst4 sncst3 sncst2 sncst1 sncst0 initial value: xxxx xxxx b address: 0be8 h msb lsb wwwwww ww snced sync-tip window end position snced7 snced6 snced5 snced4 snced3 snced2 snced1 snced0
hms81c4x60 november 2001 ver 1.1 83 18.4 data sampling line 21 closed caption signal figure 18-10 shows the closed caption signal. the signal composes color burst, clock run-in, start bit(001), 16bit ascii data with 2 parity bit. sliced raw datas are sampled by 4mhz frequency. figure 18-10 closed caption signal address assign table 18-1 shows the map of assigned buffer memory. table 18-1 address assign interrupt occurrence the slicer interrupt is occured after writing the sliced two lines data to memory buffer. signal timing figure 18-11 shows an example of variable signals, which includes vsync(vertical sync.), hsync(horizontal sync.), cvbs(composit video in), scap(slicer capacitor), run-in key and sync tip. line 21 closed caption signal run after vsync interrupt. the signals black(base) level voltage is charged on sync-tip switch-on period, and the referance voltage of comparator is charged on rik switch-on perid. because rik time is related to scap voltage(comparator referance voltage or slicer level) which is charged by clock run-in signal, user can adjust the slicer level by rik time. the sliced data is stored to ram buffer. (0600h~ 06ffh) setting address first line even field 0600h ~ 063fh odd field 0640h ~ 067fh secont line even field 0680h ~ 06bfh odd field 06c0h ~ 06ffh two (7 bit + parity ) characters ( data ) [ caption data ] start bit(001) clock run in program color burst 33.76us 51.26us 61.342us 12.91us 3.972us
hms81c4x60 84 november 2001 ver 1.1 figure 18-11 signal timing [example] initializing slicer register. ccd_init: ldm slinf0,#0011_0011b ; slicer line 21 ldm slinf1,#0000_0000b ; no field ldm rikst,#01 ; run-in key start : 1 -> 0.125us(8mhz) ldm riked,#8ch ; run-in key end : 8ch -> 17.5us(8mhz) ldm sncst,#01 ; sync tip start : 1 -> 0.0625us(16mhz) ldm snced,#58h ; sync tip end : 58h -> 5.5us(16mhz) ldm slcon,#01h ; normal clock, 16mhz, slicer start vsync hsync cvbs scap rik sync_tip 5v 5v 5v 5v 2.5v 2v 2.2v 0v 0v 5v 5v 0.5v 2 3 4 1 1 hsync cycle run-in key start/stop timming sync-tip start/stop timming slicer capacitor charging level line 21 signal
hms81c4x60 november 2001 ver 1.1 85 19. i 2 c bus interface the i 2 c bus interface circuit is shown in figure 19-1. the multi-master i 2 c bus interface is a serial communica- tions circuit, conforming to the phlips i 2 c bus data trans- fer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. this multi-master i 2 c bus interface circuit consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c sta- tus register and other control circuits. the more details about registers are shown figure 19-2~ figure 19-5. figure 19-1 block diagram of multi-master i 2 c circuit control the hms81c4x60 contains two i 2 c bus interface mod- ules. it supports multi-master function, so it contains arbi- tration lost detection, synchronization function,etc. i 2 c address register it contains slave address (7bit) which is used during slave mode and read/write bit. bit 7 ~ 1 : slave address 6~0 note: bit 7~1 (sad6~0) store slave address. the address data transmitted from the master is compared with the con- tents of these bits. icar [d8 h ] ifi2cr scl address comparator icdr [d9 h ] d7 d6 d5 d4 d3 d2 d1 d0 interrupt generation circuit data control circuit icsr [00da h ] mst trx bb pin al ad0 adrb lrb noise elimination circuit al circuit bb circuit clock control circuit noise elimination circuit iccr [00db h ] bsel1 ccr3 eso clock division clock source sda sad6 sda5 sda4 sda3 sda2 sda1 sda0 rwb bsel1 ackb ccr2 ccr1 ccr0 item function format philips i 2 c standard 7bit addressing format communication mode master transmitter master receiver slave transmitter slave receiver
hms81c4x60 86 november 2001 ver 1.1 figure 19-2 i 2 c address register i 2 c data shift register [icdr] the i 2 c data shift register is an 8bit shift register to store received data and write transmit data. when transmit data is written into this register, it is trans- fered to the outside from bit7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is re- ceived, it is input to this register from bit0 in synchroniza- tion with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00dc h ) is 1. the bit counter is reset by a write instruc- tion to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled regardless of the eso bit value. figure 19-3 data shift register i 2 c status register the i 2 c status register controls the i 2 c bus interface sta- tus. the low-order 4bits are read only bits and the high-or- der 4bits can be read out and written to. the more details about its bits are shown table 19-1. icar address : 00d8 h reset value : 0000 0000 b sad6 sda5 sda4 sda3 sda2 sda1 sda0 rwb slave address rw rw rw rw rw rw rw r read/write bit icdr address : 00d9 h reset value : 0000 0000 b rw rw rw rw rw rw rw rw d7 d6 d5 d4 d3 d2 d1 d0 shift left 1-bit each scl bit no. name function 7 6 mst trx 00: slave / receiver mode 01: slave / transmitter mode 10: master / receiver mode 11: master / transmitter mode mst is cleared when - after reset. - after the arbitration lost is occured and 1 byte data transmission is finished. - after stop condition is detected. - when start condition is disabled by start condition duplication preventation function. trx is cleared when - after reset. - when arbitration lost or stop condition is occured . - when mst is 0, and start condition or ack non-return mode is detected. 5bb bb(bus busy)bit is 1 during bus is busy. this bit can be written by s/w. its value is 1 by start condition, and cleared by stop condition. 4pin pin(pending interrupt not)bit is inter- rupt request bit. if i 2 c interrupt request is issued, its value is 0. pin is cleared when - after 1 byte trasmission / receive is fin- ished. pin is set when - after reset. - after write instruction is excuted into i 2 c data shift register icdr. - when pin bit low, the output of scl is pulled down, so if you want to release scl, you must perform write instruction cdr. 3al arbitration lost detection flag. if arbitration lost is detected, al=1, or 0. 2ad0 general call detection flag. if general call is detected, ad0=1, or not 0. * general call : if received address is all 0 . it is called general call. 1 adrb address represent flag 0 : current contents is address 1 : current contents is data
hms81c4x60 november 2001 ver 1.1 87 figure 19-4 i 2 c status register i 2 c control register it controls communication data format. it controls scl mode, scl frequency, etc. it contains 8bit data to transmit to external device when tr- asmitter mode, or received 8bit data from external device when receive mode. figure 19-5 i 2 c control register figure 19-6 interrupt request signal generation timing 0lrb last received bit. it is used for receive confirmation. if ack is returned, lrb=0, or not 1. bit no. name function table 19-1 bit function icsr address : 00da h reset value : 0001 0000 b rw rw rw rw r r r r mst trx bb pin al ad0 adrb lrb iccr address : 00db h reset value : 0000 0000 b eso ccr3 ccr2 ccr1 ccr0 bsel0 rw rw rw rw rw rw rw bsel1 ackb rw scl pin i 2 c request bit no. name function 7 6 bsel1 bsel0 i 2 c connection control. 00: no connection 01: scl0, sda0 10: scl1, sda1 11: scl0, sda0, scl1, sda1 5ack if acknowlege clock is returned, this bit is 0, or not 1. 4 eso i 2 c bus interface use enable flag 0: disabled 1: enabled 3 2 1 0 ccr3 ccr2 ccr1 ccr0 scl frequency selection scl frequency = f ex / (12 * ccr) value f ex = 4mhz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not allowed not allowed 333.3khz 222.2khz 166.6khz 133.3khz 111.1khz 95.2khz 83.3khz 74.1khz 66.6khz 60.6khz 55.5khz 51.3khz 47.6khz 44.4khz table 19-2 bit function
hms81c4x60 88 november 2001 ver 1.1 start condition generation when the eso bit of the i 2 c control register (00db h ) is 1, writing to the i 2 c status register will generate start condition. refer to figure 19-7 for the start condition generation timing diagram. figure 19-7 start condition generation timing restart condition generation restart conditions setting sequence is as followings. 1. write 020 h to i 2 c status register (icsr, 00da h ) 2. write slave address to i 2 c data shift register (icdr, 00d9 h ) 3. write 0f0 h to i 2 c status register (icsr, 00da h ) stop condition generation writing c0h to icsr will generate a stop condition, w h e n e s o ( i c c r b i t 3 ) i s 1 figure 19-8 stop condition generating timing diagram start / stop condition generation time is shown table 19-3. icsr write signal scl sda bb (bus busy) flag t setup t hold t bb : setup time : hold time : set time for bb t setup t hold t bb (i 2 c status reg.) item timing spec. setup time ( t setup ) 3.3us (n=20cycles) hold time ( t hold ) 3.3us (n=20cycles) set/reset time for bb flag ( t bb ) 3.0us (n=18cycles) table 19-3 example time ( f ex =4mhz ) icsr write signal scl sda bb (bus busy) flag t setup t hold t bb : setup time : hold time : set time for bb t setup t hold t bb (i 2 c status reg.)
hms81c4x60 november 2001 ver 1.1 89 start / stop condition detect start / stop condition is detected when table 19-3 is satisfied. figure 19-9 start / stop condition detection timing start / stop detection time is showed table 19-4. address data communication the first transmitted data from master is compared with i 2 c address register (icar, 00d8 h ). at this time r/w is not compared but it determines next data operation. i.e, transmitting or receiving data figure 19-10 address data communication format scl sda (start) sda (stop) t setup t hold : setup time : hold time t setup t hold scl release time item timing spec. scl release time > 2.0us (n=12cycles) setup time > 1.0us (n=6cycles) hold time > 1.0us (n=6cycles) table 19-4 example time ( f ex =4mhz ) master -> slave (with 7bit address) start r/w ack ack ack /ack data stop slave addr. slave -> master (with 7bit address) data block from master to slave data block from slave to master 7bit data start r/w ack ack ack data stop slave addr. 7bit data (1) (0)
hms81c4x60 90 november 2001 ver 1.1 20. watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and re- sumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. figure 20-1 block diagram of watchdog timer watchdog timer control figure 20-2 shows the watchdog timer control register. the watchdog timer is automatically disabled after reset. the cpu malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. re- peatedly clearing the binary counter within the setting de- tection time. if the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter are cleared. at this time, when wdton=1 a reset is generated, which drives the reset pin low to reset the internal hardware. when wdton=0, a watchdog timer interrupt (ifwdt) is generated. figure 20-2 watchdog timer register to reset cpu wdtr watchdog timer register (bit overflow : ifbit) clock source 6-bit up-counter enable wdt 6-bit compare data comparator 6 wdtr[bit5~0] watchdog timer interrupt wdtcl[bit6] clear [00d7 h ] ifwdt ckctlr clock control register [00d6 h ] wdton[bit5] ckctlr address : 00d6 h reset value : 0000 0000 b wdt enp btcl bts2 bts1 bts0 watchdog timer on/off control w w wwwr wdtr address : 00d7 h reset value : -011 1111 b wdt wdtr5 ~ 0 slave address ww w wwww on ck 0: normal 6bit timer, watchdog off 1: watchdog timer cl watchdog timer clear 0: watchdog timer free run 1: watchdog timer clear and free run automatically cleared this bit after 1cycle
hms81c4x60 november 2001 ver 1.1 91 example: sets the watchdog timer detection time enable and disable watchdog watchdog timer is enabled by setting wdton (bit 5 in cktclr) to "1". wdton is initialized to "0" during re- set, wdton should be set to "1" to operate after reset is released. example: enables watchdog timer reset : ldm cktclr,#001?????b ;wdton ? 1 : : the watchdog timer is disabled by clearing bit 5 (wd- ton) of cktclr. watchdog timer interrupt the watchdog timer can also be used as a simple 6-bit tim- er by clearing bit 5 (wdton) of cktclr. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 6-bit timer interrupt setting up. ldx #03fh txsp ;sp ? 3f ldm cktclr,#000?????b ;wdton ? 0 ldm wdtr,#01??????b ;wdtcl ? 0 : : refer table and see bit timer (). ldm wdtr,#01??????b ; clear counter and set value(??????b) ; you have to set wdtr first, for prevent unpredictable interrupt ; when you set wdton bit. ldm ckctlr,#00111???b ; select clock source(???b) and wdton=1 ldm wdtr,#01??????b ; clear counter : : : : ldm wdtr,#01??????b ; clear counter : : : : ldm wdtr,#01??????b ; clear counter within wdt detection time within wdt detection time t wdtr interval of bit = ckctlr bts2~0 bit input clock watchdog timer input clock ifwdt cycle 000 b ps4 (4us) 1,024us 32,256us 001 b ps5 (8us) 2,028us 64,512us 010 b ps6 (16us) 4,096us 129,024us 011 b ps7 (32us) 8,192us 258,048us 100 b ps8 (64us) 16,384us 516,096us 101 b ps9 (128us) 32,768us 1,032,192us 110 b ps10 (256us) 65,536us 2,064,384us 111 b ps11 (512us) 131,072us 4,128,768us table 20-1 watchdog timer max. cycle (ex:f ex =4mhz)
hms81c4x60 92 november 2001 ver 1.1 figure 20-3 watchdog timer timing minimizing current consumption it should be set properly that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. see figure 20-4. 2 3 n source clock binary-counter wdtr ifwdt interrupt wdtr ? "0100_0011b" 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
hms81c4x60 november 2001 ver 1.1 93 figure 20-4 application example of port under power consumption input pin v dd gnd i v dd output pin gnd i x weak pull-up current flows in the left case, much current flows from port to gnd. x on off v dd internal pull-up output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, low output to the port . input pin i v dd x very weak current flows v dd o o open on off open i=0 o o v dd o i=0 o gnd o when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption.
hms81c4x60 94 november 2001 ver 1.1 21. oscillator circuit the hms81c4x60 has two oscillation circuits internally. x in and x out are input and output for main frequency and osc1 and osc2 are input and output for osd(on screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 21-1 . figure 21-1 oscillation circuit oscillation components have their own characteristics, so user should consult the component manufacturers for ap- propriate values of external components. in addition, see figure 21-2 for the layout of the crystal. note: minimize the wiring length. do not allow wiring to in- tersect with other signal conductors. do not allow wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. figure 21-2 layout example of oscillator pcb circuit x out x in v ss recommend c1 c2 x out x in external clock open external oscillator crystal oscillator fc (mhz) fc (mhz) 4 c1 & c2 (pf) 15 x out x in
hms81c4x60 november 2001 ver 1.1 95 22. reset the hms81c4x60 have two types of reset generation pro- cedures; one is an external reset input, other is a watch-dog timer reset. table 22-1 shows on-chip hardware initializa- tion by reset action. table 22-1 initializing internal status by reset action 22.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is ap- plied and the internal state is initialized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 22-2 . internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before reading or testing it. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffe h - ffff h . a connecting for simple power-on-reset is shown in figure 22-1 . figure 22-1 simple power-on-reset circuit figure 22-2 timing diagram after reset on-chip hardware initial value on-chip hardware initial value program counter pc (ffff h ) - (fffe h ) peripheral clock off ram page register dpgr 00 h watchdog timer disable g-flag of psw g 0 control registers refer to table 8-1 on page 22 reset + - v dd gnd mcu main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1 fetch ~ ~
hms81c4x60 96 november 2001 ver 1.1 22.2 watchdog timer reset refer to 20. watchdog timer on page 90.
hms81c4x60 november 2001 ver 1.1 97 23. otp programming 23.1 hms87c4x60 otp programming user can burn out hms87c4x60 otp through the general gang programmer using special rom writer. in devleop- ment tool package auxiliary, hms87c4x60 has rom writer socket. hms87c4x60 have two rom memory ar- eas. one is program rom memory and the other is font rom memory. program rom area is from 1000h to ffffh font rom area is from 10000h to 17fffh. blank check figure 23-1 hms87c4x60 otp memory map program writing there are two kind of otp file. one is program otp file(***.otp) and the other is font otp file(***.fnt). you can make each file through asmlinker.exe and osdfont.exe respectively. all otp file is motolora s- format. you can burn the program file and font file respec- tively or together. to burn program file and font file re- spectively, refer following procedure 1. make program otp file and font otp file repec- tively. 2. burn program otp file(set chip target address 1000h ~ ffffh) 3. burn font otp file(set chip target address 10000h ~17fffh) to burn program file and font file together, refer following procedure 1. add program otp file and font otp file 2. burn otp file(set chip target address 1000h ~ 17fffh) about other details, refer rom wirter manual. 1000h ffffh 17fffh osd font memory program memory
hms81c4x60 98 november 2001 ver 1.1 23.2 .device configuration data figure 23-2 figure pin configuration in otp programming mode figure 23-3 figure mode table hynix hms87c4260 om1 om2 om3 pgmb dio<4> dio<2> dio<3> oeb ceb ahb alb 32sdip dio<1> dio<0> dio<6> dio<5> vpp a16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 dio<7> hms87c4x60 mode vpp ceb oeb pgmb program 11.25 low high low verify 11.25 low low high optional verify 5 low low x gang write 11.25 low high low gang verify 11.25, 5 low low x
hms81c4x60 november 2001 ver 1.1 99 24. assemble mnemonics 24.1 instruction map 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 nop set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc // // // sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg // // // cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di // // // or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv // // // and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc // // // eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg // // // lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei // // // ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xas 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel // // // sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel // // // cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel // // // or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel // // // and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel // // // eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel // // // lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel // // // sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
hms81c4x60 100 november 2001 ver 1.1 24.2 alphabetic order table of instruction no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 10 and #imm 84 2 2 logical and n - - - - - z - 11 and dp 85 2 3 a ? a ^ (m) 12 and dp + x 86 2 4 13 and !abs 87 3 4 14 and !abs+y 95 3 5 15 and [dp+x] 96 2 6 16 and [dp] + y 97 2 6 17 and {x} 94 1 3 18 and1 m.bit 8b 3 4 bit and c-flag : c ? c ^ (m.bit) - - - - - - - c 19 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c ^ ~(m.bit) - - - - - - - c 20 asl a 08 1 2 arithmetic shift left n - - - - - zc 21 asl dp 09 2 4 22 asl dp + x 19 2 5 23 asl !abs 18 3 5 24 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 25 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 26 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 27 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 28 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 29 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 30 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 31 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 32 bit !abs 1c 3 5 z ? a ^ m, n ? (m 7 ), v ? (m 6 ) 33 bmi rel 90 2 2/4 branch if munus : if (n) = 1, then pc ? pc + rel - - - - - - - - 34 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 35 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 36 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 37 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 38 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 39 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel 40 call !abs 3b 3 8 subroutine call - - - - - - - - 41 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) 42 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 43 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 44 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 45 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 46 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 47 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
hms81c4x60 november 2001 ver 1.1 101 48 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 49 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 50 cmp dp 45 2 3 a - (m) 51 cmp dp + x 46 2 4 52 cmp !abs 47 3 4 53 cmp !abs + y 55 3 5 54 cmp [dp + x] 56 2 6 55 cmp [dp] + y 57 2 6 56 cmp {x} 54 1 3 57 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 58 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 59 cmpx dp 6c 2 3 x - (m) 60 cmpx !abs 7c 3 4 61 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 62 cmpy dp 8c 2 3 y - (m) 63 cmpy !abs 9c 3 4 64 com dp 2c 2 4 1s complement : (dp) ? ~(dp) n - - - - - z - 65 daa df 1 3 decimal adjust for addition n - - - - - zc 66 das cf 1 3 decimal adjust for substraction n - - - - - zc 67 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 68 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 69 dec a a8 1 2 decrement n - - - - - z - 70 dec dp a9 2 4 m ? m - 1 71 dec dp + x b9 2 5 72 dec !abs b8 3 5 73 dec x af 1 2 74 dec y be 1 2 75 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 76 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 77 div 9b 1 12 divide : ya / x ? q:a, r:y nv - - h - z - 78 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 79 eor #imm a4 2 2 exclusive or n - - - - - z - 80 eor dp a5 2 3 a ? a ? (m) 81 eor dp + x a6 2 4 82 eor !abs a7 3 4 83 eor !abs + y b5 3 5 84 eor [ dp + x] 96 2 6 85 eor [dp] + y 97 2 6 86 eor {x} 94 1 3 87 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 88 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? ~ (m.bit) - - - - - - - c 89 inc a 88 1 2 increment n - - - - - zc 90 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 91 inc dp + x 99 2 5 92 inc !abs 98 3 5 93 inc x 8f 1 2 94 inc y 9e 1 2 95 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z - 96 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 97 jmp [!abs] 1f 3 5 pc ? jump address 98 jmp [dp] 3f 2 4 no. mnenonic op code byte no. cycle no operation flag nvgbhizc
hms81c4x60 102 november 2001 ver 1.1 99 lda #imm c4 2 2 load accumulator n - - - - - z - 100 lda dp c5 2 3 a ? (m) 101 lda dp + x c6 2 4 102 lda !abs c7 3 4 103 lda !abs + y d5 3 5 104 lda [dp + x] d6 2 6 105 lda [dp]+y d7 2 6 106 lda {x} d4 1 3 107 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 108 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 109 ldcb m.bit cb 3 4 load c-flag with not : c ? ~(m.bit) - - - - - - - c 110 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 111 ldx #imm 1e 2 2 load x-register n - - - - - z - 112 ldx dp cc 2 3 x ? (m) 113 ldx dp + y cd 2 4 114 ldx !abs dc 3 4 115 ldy #imm 3e 2 2 load x-register n - - - - - z - 116 ldy dp c9 2 3 y ? (m) 117 ldy dp + y d9 2 4 118 ldy !abs d8 3 4 119 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 120 lsr a 48 1 2 logical shift right n - - - - - zc 121 lsr dp 49 2 4 122 lsr dp + x 59 2 5 123 lsr !abs 58 3 5 124 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 125 nop 00,ff 1 2 no operation - - - - - - - - 126 not1 m.bit 4b 3 5 bit complement : (m.bit) ? ~(m.bit) - - - - - - - - 127 or #imm 64 2 2 logical or n - - - - - z - 128 or dp 65 2 3 a ? a v (m) 129 or dp + x 66 2 4 130 or !abs 67 3 4 131 or !abs + y 75 3 5 132 or [dp +x} 76 2 6 133 or [dp] + y 77 2 6 134 or {x} 74 1 3 135 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 136 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v ~(m.bit) - - - - - - - c 137 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " 138 pop a 0d 1 4 pop from stack - - - - - - - - 139 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 140 pop y 4d 1 4 141 pop psw 6d 1 4 (restored) 142 push a 0e 1 4 push to stack - - - - - - - - 143 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 144 push y 4e 1 4 145 push psw 6e 1 4 146 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 147 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp) no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ?
hms81c4x60 november 2001 ver 1.1 103 148 rol a 28 1 2 rotate left through carry n - - - - - zc 149 rol dp 29 2 4 150 rol dp + x 39 2 5 151 rol !abs 38 3 5 152 ror a 68 1 2 rotate right through carry n - - - - - zc 153 ror dp 69 2 4 154 ror dp + x 79 2 5 155 ror !abs 78 3 5 156 sbc #imm 24 2 2 substract with carry nv - - hzc 157 sbc dp 25 2 3 a ? a - (m) - ~(c) 158 sbc dp + x 26 2 4 159 sbc !abs 27 3 4 160 sbc !abs + y 35 3 5 161 sbc [dp + x] 36 2 6 162 sbc [dp] + y 37 2 6 163 sbc {x} 34 1 3 164 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 165 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 166 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 167 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 168 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 169 sta dp + x e6 2 4 (m) ? a 170 sta !abs e7 3 4 171 sta !abs + y f5 3 5 172 sta [dp + x] f6 2 6 173 sta [dp] + y f7 2 6 174 sta {x} f4 1 3 175 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 176 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 177 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 178 stx dp + y ed 2 5 (m) ? x 179 stx !abs fc 3 5 180 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 181 sty dp + x f9 2 5 (m) ? y 182 sty !abs f8 3 5 183 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 184 subw dp 3d 2 5 16-bits substract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc 185 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 186 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 187 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h) 188 tclr1 !abs 5c 3 6 test and clear bits with a : n - - - - - z - a - (m), (m) ? (m) ^ ~(a) 189 tset1 !abs 3c 3 6 test and set bits with a : n - - - - - z - a - (m), (m) ? (m) v (a) 190 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 191 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 192 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 193 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 194 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 195 xax ee 1 4 exchange x-register contents with accumulator : x f a - - - - - - - - 196 xay de 1 4 exchange y-register contents with accumulator : y f a - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
hms81c4x60 104 november 2001 ver 1.1 24.3 instruction table by function 1. arithmetic/logic operation 197 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 f a 3 ~ a 0 198 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 199 xma dp + x ad 2 6 (m) f a 200 xma {x} bb 1 5 201 xyx fe 1 4 exchange x-register contents with y-register : x f y - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 and #imm 84 2 2 logical and n - - - - - z - 10 and dp 85 2 3 a ? a ^ (m) 11 and dp + x 86 2 4 12 and !abs 87 3 4 13 and !abs+y 95 3 5 14 and [dp+x] 96 2 6 15 and [dp] + y 97 2 6 16 and {x} 94 1 3 17 asl a 08 1 2 arithmetic shift left n - - - - - zc 18 asl dp 09 2 4 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 22 cmp dp 45 2 3 a - (m) 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 25 cmp !abs + y 55 3 5 26 cmp [dp + x] 56 2 6 27 cmp [dp] + y 57 2 6 28 cmp {x} 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 30 cmpx dp 6c 2 3 x - (m) 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 33 cmpy dp 8c 2 3 y - (m) 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : (dp) ? ~(dp) n - - - - - z - 36 daa df 1 3 decimal adjust for addition n - - - - - zc 37 das cf 1 3 decimal adjust for substraction n - - - - - zc 38 dec a a8 1 2 decrement n - - - - - z - 39 dec dp a9 2 4 m ? m - 1 40 dec dp + x b9 2 5 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
hms81c4x60 november 2001 ver 1.1 105 44 div 9b 1 12 divide : ya / x ? q:a, r:y nv - - h - z - 45 eor #imm a4 2 2 exclusive or n - - - - - z - 46 eor dp a5 2 3 a ? a ? (m) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 49 eor !abs + y b5 3 5 50 eor [ dp + x] 96 2 6 51 eor [dp] + y 97 2 6 52 eor {x} 94 1 3 53 inc a 88 1 2 increment n - - - - - zc 54 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 55 inc dp + x 99 2 5 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 logical shift right n - - - - - zc 60 lsr dp 49 2 4 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 64 or #imm 64 2 2 logical or n - - - - - z - 65 or dp 65 2 3 a ? a v (m) 66 or dp + x 66 2 4 67 or !abs 67 3 4 68 or !abs + y 75 3 5 69 or [dp +x} 76 2 6 70 or [dp] + y 77 2 6 71 or {x} 74 1 3 72 rol a 28 1 2 rotate left through carry n - - - - - zc 73 rol dp 29 2 4 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry n - - - - - zc 77 ror dp 69 2 4 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 substract with carry nv - - hzc 81 sbc dp 25 2 3 a ? a - (m) - ~(c) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 84 sbc !abs + y 35 3 5 85 sbc [dp + x] 36 2 6 86 sbc [dp] + y 37 2 6 87 sbc {x} 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 89 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 f a 3 ~ a 0 no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ? c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
hms81c4x60 106 november 2001 ver 1.1 2. register / memory operation 3. 16-bit operation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator n - - - - - z - 2 lda dp c5 2 3 a ? (m) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 6 lda [dp + x] d6 2 6 7 lda [dp]+y d7 2 6 8lda {x} d4 1 3 9 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 11 ldx #imm 1e 2 2 load x-register n - - - - - z - 12 ldx dp cc 2 3 x ? (m) 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load x-register n - - - - - z - 16 ldy dp c9 2 3 y ? (m) 17 ldy dp + y d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 20 sta dp + x e6 2 4 (m) ? a 21 sta !abs e7 3 4 22 sta !abs + y f5 3 5 23 sta [dp + x] f6 2 6 24 sta [dp] + y f7 2 6 25 sta {x} f4 1 3 26 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 28 stx dp + y ed 2 5 (m) ? x 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 31 sty dp + x f9 2 5 (m) ? y 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 36 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 37 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 38 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 39 xax ee 1 4 exchange x-register contents with accumulator : x f a - - - - - - - - 40 xay de 1 4 exchange y-register contents with accumulator : y f a - - - - - - - - 41 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 42 xma dp + x ad 2 6 (m) f a 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x f y - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 3 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 4 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z -
hms81c4x60 november 2001 ver 1.1 107 4. bit manipulation 5. branch / jump operation 5 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 6 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 7 subw dp 3d 2 5 16-bits substract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? c ^ (m.bit) - - - - - - - c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c ^ ~(m.bit) - - - - - - - c 3 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 4 bit !abs 1c 3 5 z ? a ^ m, n ? (m 7 ), v ? (m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 6 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 7 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 8 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - 9 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? ~ (m.bit) - - - - - - - c 12 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~(m.bit) - - - - - - - c 14 not1 m.bit 4b 3 5 bit complement : (m.bit) ? ~(m.bit) - - - - - - - - 15 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v ~(m.bit) - - - - - - - c 17 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 18 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 19 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 20 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 21 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 22 tclr1 !abs 5c 3 6 test and clear bits with a : n - - - - - z - a - (m), (m) ? (m) ^ ~(a) 23 tset1 !abs 3c 3 6 test and set bits with a : n - - - - - z - a - (m), (m) ? (m) v (a) no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 2 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 4 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 5 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 6 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 7 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 8 bmi rel 90 2 2/4 branch if munus : if (n) = 1, then pc ? pc + rel - - - - - - - - 9 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 10 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 11 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 12 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 13 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel
hms81c4x60 108 november 2001 ver 1.1 6. control operation & etc. 14 call !abs 3b 3 8 subroutine call - - - - - - - - 15 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) 16 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 17 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 19 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 20 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 21 jmp [!abs] 1f 3 5 pc ? jump address 22 jmp [dp] 3f 2 4 23 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " 24 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h) no. mnenonic op code byte no. cycle no operation flag nvgbhizc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 2 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 3 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 4 nop ff 1 2 no operation - - - - - - - - 5 pop a 0d 1 4 pop from stack - - - - - - - - 6 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 7 pop y 4d 1 4 8 pop psw 6d 1 4 (restored) 9 push a 0e 1 4 push to stack - - - - - - - - 10 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 11 push y 4e 1 4 12 push psw 6e 1 4 13 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 14 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp)

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